Struct stm32_metapac::rcc::regs::Apb7rstr
#[repr(transparent)]pub struct Apb7rstr(pub u32);
Expand description
RCC APB7 peripheral reset register
Tuple Fields§
§0: u32
Implementations§
§impl Apb7rstr
impl Apb7rstr
pub const fn syscfgrst(&self) -> bool
pub const fn syscfgrst(&self) -> bool
SYSCFG reset Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_syscfgrst(&mut self, val: bool)
pub fn set_syscfgrst(&mut self, val: bool)
SYSCFG reset Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn spi3rst(&self) -> bool
pub const fn spi3rst(&self) -> bool
SPI3 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_spi3rst(&mut self, val: bool)
pub fn set_spi3rst(&mut self, val: bool)
SPI3 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn lpuart1rst(&self) -> bool
pub const fn lpuart1rst(&self) -> bool
LPUART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_lpuart1rst(&mut self, val: bool)
pub fn set_lpuart1rst(&mut self, val: bool)
LPUART1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn i2c3rst(&self) -> bool
pub const fn i2c3rst(&self) -> bool
I2C3 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_i2c3rst(&mut self, val: bool)
pub fn set_i2c3rst(&mut self, val: bool)
I2C3 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn lptim1rst(&self) -> bool
pub const fn lptim1rst(&self) -> bool
LPTIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_lptim1rst(&mut self, val: bool)
pub fn set_lptim1rst(&mut self, val: bool)
LPTIM1 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.