Struct stm32_metapac::rcc::regs::Apb1smenr2
#[repr(transparent)]pub struct Apb1smenr2(pub u32);
Expand description
RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2
Tuple Fields§
§0: u32
Implementations§
§impl Apb1smenr2
impl Apb1smenr2
pub const fn lptim2smen(&self) -> bool
pub const fn lptim2smen(&self) -> bool
LPTIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
pub fn set_lptim2smen(&mut self, val: bool)
pub fn set_lptim2smen(&mut self, val: bool)
LPTIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
Trait Implementations§
§impl Clone for Apb1smenr2
impl Clone for Apb1smenr2
§fn clone(&self) -> Apb1smenr2
fn clone(&self) -> Apb1smenr2
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read more§impl Default for Apb1smenr2
impl Default for Apb1smenr2
§fn default() -> Apb1smenr2
fn default() -> Apb1smenr2
§impl PartialEq for Apb1smenr2
impl PartialEq for Apb1smenr2
§fn eq(&self, other: &Apb1smenr2) -> bool
fn eq(&self, other: &Apb1smenr2) -> bool
self
and other
values to be equal, and is used
by ==
.