Struct stm32_metapac::syscfg::regs::Cfgr2
#[repr(transparent)]pub struct Cfgr2(pub u32);
Expand description
configuration register 2
Tuple Fields§
§0: u32
Implementations§
§impl Cfgr2
impl Cfgr2
pub const fn cll(&self) -> bool
pub const fn cll(&self) -> bool
Cortex-M33 LOCKUP (hardfault) output enable This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input.
pub fn set_cll(&mut self, val: bool)
pub fn set_cll(&mut self, val: bool)
Cortex-M33 LOCKUP (hardfault) output enable This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input.
pub const fn spl(&self) -> bool
pub const fn spl(&self) -> bool
SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs.
pub fn set_spl(&mut self, val: bool)
pub fn set_spl(&mut self, val: bool)
SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs.
pub const fn pvdl(&self) -> bool
pub const fn pvdl(&self) -> bool
PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register.
pub fn set_pvdl(&mut self, val: bool)
pub fn set_pvdl(&mut self, val: bool)
PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register.