Struct stm32_metapac::flash::regs::Acr

#[repr(transparent)]
pub struct Acr(pub u32);

Expand description

access control register

Tuple Fields§

§0: u32

Implementations§

§

impl Acr

pub const fn latency(&self) -> u8

Latency These bits represent the ratio between the AHB hclk1 clock period and the memory access time. Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. … Note: Before entering Stop 1 mode software must set wait state latency to at least 1.

pub fn set_latency(&mut self, val: u8)

Latency These bits represent the ratio between the AHB hclk1 clock period and the memory access time. Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. … Note: Before entering Stop 1 mode software must set wait state latency to at least 1.

pub const fn prften(&self) -> bool

Prefetch enable This bit enables the prefetch buffer in the embedded memory. This bit can be protected against unprivileged access by NSPRIV.

pub fn set_prften(&mut self, val: bool)

Prefetch enable This bit enables the prefetch buffer in the embedded memory. This bit can be protected against unprivileged access by NSPRIV.

pub const fn lpm(&self) -> bool

Low-power read mode This bit puts the memory in low-power read mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected.

pub fn set_lpm(&mut self, val: bool)

Low-power read mode This bit puts the memory in low-power read mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. This bit can’t be written when a program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a program or erase operation is busy (BSY = 1) is rejected.

pub const fn pdreq(&self) -> bool

power-down mode request This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked. This bit is write-protected with PDKEYR. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

pub fn set_pdreq(&mut self, val: bool)

power-down mode request This bit requests to enter power-down mode. When enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked. This bit is write-protected with PDKEYR. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

pub const fn sleep_pd(&self) -> bool

memory power-down mode during Sleep mode This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. The must not be put in power-down while a program or an erase operation is ongoing.

pub fn set_sleep_pd(&mut self, val: bool)

memory power-down mode during Sleep mode This bit determines whether the memory is in power-down mode or Idle mode when the device is in Sleep mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV. The must not be put in power-down while a program or an erase operation is ongoing.