Struct stm32_metapac::flash::regs::Seccr1

#[repr(transparent)]
pub struct Seccr1(pub u32);

Expand description

secure control register

Tuple Fields§

§0: u32

Implementations§

§

impl Seccr1

pub const fn pg(&self) -> bool

Secure programming

pub fn set_pg(&mut self, val: bool)

Secure programming

pub const fn per(&self) -> bool

Secure page erase

pub fn set_per(&mut self, val: bool)

Secure page erase

pub const fn mer(&self) -> bool

Secure mass erase This bit triggers the secure mass erase (all user pages) when set.

pub fn set_mer(&mut self, val: bool)

Secure mass erase This bit triggers the secure mass erase (all user pages) when set.

pub const fn pnb(&self) -> u8

Secure page number selection These bits select the page to erase: … Note that bit 9 is reserved on STM32WBA5xEx devices.

pub fn set_pnb(&mut self, val: u8)

Secure page number selection These bits select the page to erase: … Note that bit 9 is reserved on STM32WBA5xEx devices.

pub const fn bwr(&self) -> bool

Secure burst write programming mode When set, this bit selects the burst write programming mode.

pub fn set_bwr(&mut self, val: bool)

Secure burst write programming mode When set, this bit selects the burst write programming mode.

pub const fn strt(&self) -> bool

Secure start This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in SECSR.

pub fn set_strt(&mut self, val: bool)

Secure start This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in SECSR.

pub const fn eopie(&self) -> bool

Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in SECSR is set to 1.

pub fn set_eopie(&mut self, val: bool)

Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in SECSR is set to 1.

pub const fn errie(&self) -> bool

Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1.

pub fn set_errie(&mut self, val: bool)

Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in SECSR is set to 1.

pub const fn inv(&self) -> bool

memory security state invert This bit inverts the memory security state.

pub fn set_inv(&mut self, val: bool)

memory security state invert This bit inverts the memory security state.

pub const fn lock(&self) -> bool

Secure lock This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.

pub fn set_lock(&mut self, val: bool)

Secure lock This bit is set only. When set, the SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset.