Expand description
§cyw43-pio
RP2040 PIO driver for the nonstandard half-duplex SPI used in the Pico W. The PIO driver offloads SPI communication with the WiFi chip and improves throughput.
Structs§
- PioSpi
- SPI comms driven by PIO.
Constants§
- DEFAULT_
CLOCK_ DIVIDER - Clock divider used for most applications With default core clock configuration: RP2350: 150Mhz / 2 = 75Mhz pio clock -> 37.5Mhz GSPI clock RP2040: 133Mhz / 2 = 66.5Mhz pio clock -> 33.25Mhz GSPI clock
- OVERCLOCK_
CLOCK_ DIVIDER - Clock divider used to overclock the cyw43 With default core clock configuration: RP2350: 150Mhz / 1 = 150Mhz pio clock -> 75Mhz GSPI clock (50% greater that manufacturer recommended 50Mhz) RP2040: 133Mhz / 1 = 133Mhz pio clock -> 66.5Mhz GSPI clock (33% greater that manufacturer recommended 50Mhz)
- RM2_
CLOCK_ DIVIDER - Clock divider used with the RM2 With default core clock configuration: RP2350: 150Mhz / 3 = 50Mhz pio clock -> 25Mhz GSPI clock RP2040: 133Mhz / 3 = 44.33Mhz pio clock -> 22.16Mhz GSPI clock