Crate cyw43_pio

cyw43-pio

RP2040 PIO driver for the nonstandard half-duplex SPI used in the Pico W. The PIO driver offloads SPI communication with the WiFi chip and improves throughput.

Structs

• PioSpi
  SPI comms driven by PIO.

Constants

• DEFAULT_CLOCK_DIVIDER
  The default clock divider that works for Pico 1 and 2 W. As well as the RM2 on rp2040 devices. same speed as pico-sdk, 62.5Mhz This is actually the fastest we can go without overclocking. According to data sheet, the theoretical maximum is 100Mhz Pio => 50Mhz SPI Freq. However, the PIO uses a fractional divider, which works by introducing jitter when the divider is not an integer. It does some clocks at 125mhz and others at 62.5mhz so that it averages out to the desired frequency of 100mhz. The 125mhz clock cycles violate the maximum from the data sheet.
• OVERCLOCK_CLOCK_DIVIDER
  The overclock clock divider for the Pico 1 W. Does not work on any known RM2 devices. 125mhz Pio => 62.5Mhz SPI Freq. 25% higher than theoretical maximum according to data sheet, but seems to work fine.
• RM2_CLOCK_DIVIDER
  The clock divider for the RM2 module. Found to be needed for the Pimoroni Pico Plus 2 W, Pico Plus 2 Non w with the RM2 breakout module, and the Pico 2 with the RM2 breakout module.