Struct PioSpi

pub struct PioSpi<'d, PIO: Instance, const SM: usize, DMA> { /* private fields */ }

SPI comms driven by PIO.

Implementations

impl<'d, PIO, const SM: usize, DMA> PioSpi<'d, PIO, SM, DMA>

where DMA: Channel, PIO: Instance,

pub fn new<DIO, CLK>( common: &mut Common<'d, PIO>, sm: StateMachine<'d, PIO, SM>, irq: Irq<'d, PIO, 0>, cs: Output<'d>, dio: DIO, clk: CLK, dma: impl Peripheral<P = DMA> + 'd, ) -> Self

where DIO: PioPin, CLK: PioPin,

Create a new instance of PioSpi.

pub async fn write(&mut self, write: &[u32]) -> u32

Write data to peripheral and return status.

pub async fn cmd_read(&mut self, cmd: u32, read: &mut [u32]) -> u32

Send command and read response into buffer.

Trait Implementations

impl<'d, PIO, const SM: usize, DMA> SpiBusCyw43 for PioSpi<'d, PIO, SM, DMA>

where PIO: Instance, DMA: Channel,

async fn cmd_write(&mut self, write: &[u32]) -> u32

Issues a write command on the bus First 32 bits of word are expected to be a cmd word

async fn cmd_read(&mut self, write: u32, read: &mut [u32]) -> u32

Issues a read command on the bus write is expected to be a 32 bit cmd word read will contain the response of the device Backplane reads have a response delay that produces one extra unspecified word at the beginning of read. Callers that want to read n word from the backplane, have to provide a slice that is n+1 words long.

async fn wait_for_event(&mut self)

Wait for events from the Device. A typical implementation would wait for the IRQ pin to be high. The default implementation always reports ready, resulting in active polling of the device.