Struct PioSpi 

pub struct PioSpi<'d, PIO: Instance, const SM: usize> { /* private fields */ }

SPI comms driven by PIO.

Implementations

impl<'d, PIO, const SM: usize> PioSpi<'d, PIO, SM>

where PIO: Instance,

pub fn new( common: &mut Common<'d, PIO>, sm: StateMachine<'d, PIO, SM>, clock_divider: u32, irq: Irq<'d, PIO, 0>, cs: Output<'d>, dio: Peri<'d, impl PioPin>, clk: Peri<'d, impl PioPin>, dma_tx: Channel<'d, Async>, dma_rx: Channel<'d, Async>, ) -> Self

Create a new instance of PioSpi.

clock_divider is the PIO clock divider as a fixed-point number with 16 integer bits and 8 fractional bits (the divider multiplied by 256), see DEFAULT_CLOCK_DIVIDER.

pub async fn write(&mut self, write: &[u32]) -> u32

Write data to peripheral and return status.

pub async fn cmd_read(&mut self, cmd: u32, read: &mut [u32]) -> u32

Send command and read response into buffer.

Trait Implementations

impl<'d, PIO, const SM: usize> SpiBusCyw43 for PioSpi<'d, PIO, SM>

where PIO: Instance,

async fn cmd_write(&mut self, write: &[u32]) -> u32

Issues a write command on the bus First 32 bits of word are expected to be a cmd word

async fn cmd_read(&mut self, write: u32, read: &mut [u32]) -> u32

Issues a read command on the bus write is expected to be a 32 bit cmd word read will contain the response of the device Backplane reads have a response delay that produces one extra unspecified word at the beginning of read. Callers that want to read n word from the backplane, have to provide a slice that is n+1 words long.

async fn prepare_reset(&mut self)

Called immediately before the device is power-cycled, to setup bus/pins to the correct state required during reset.

async fn wait_for_event(&mut self)

Wait for events from the Device. A typical implementation would wait for the IRQ pin to be high. The default implementation always reports ready, resulting in active polling of the device.