pub const OVERCLOCK_CLOCK_DIVIDER: FixedU32<U8>;Expand description
Clock divider used to overclock the cyw43 With default core clock configuration: RP2350: 150Mhz / 1 = 150Mhz pio clock -> 75Mhz GSPI clock (50% greater that manufacturer recommended 50Mhz) RP2040: 133Mhz / 1 = 133Mhz pio clock -> 66.5Mhz GSPI clock (33% greater that manufacturer recommended 50Mhz)