Struct embassy_net_adin1110::ADIN1110

pub struct ADIN1110<SPI> { /* private fields */ }

ADIN1110 embassy-net driver

Implementations

impl<SPI: SpiDevice> ADIN1110<SPI>

pub fn new(spi: SPI, spi_crc: bool, append_fcs_on_tx: bool) -> Self

Create a new ADIN1110 instance.

pub async fn read_reg(&mut self, reg: sr) -> AEResult<u32, SPI::Error>

Read a SPI register

pub async fn write_reg( &mut self, reg: sr, value: u32 ) -> AEResult<(), SPI::Error>

Write a SPI register

pub async fn read_fifo( &mut self, frame: &mut [u8] ) -> AEResult<usize, SPI::Error>

Read out fifo ethernet packet memory received via the wire.

pub async fn write_fifo(&mut self, frame: &[u8]) -> AEResult<(), SPI::Error>

Write to fifo ethernet packet memory send over the wire.

pub async fn set_mac_addr(&mut self, mac: &[u8; 6]) -> AEResult<(), SPI::Error>

Programs the mac address in the mac filters. Also set the boardcast address. The chip supports 2 priority queues but current code doesn’t support this mode.

Trait Implementations

impl<SPI: Debug> Debug for ADIN1110<SPI>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<SPI: SpiDevice> MdioBus for ADIN1110<SPI>

async fn read_cl22(&mut self, phy_id: u8, reg: u8) -> Result<u16, Self::Error>

Read from the PHY Registers as Clause 22.

async fn read_cl45( &mut self, phy_id: u8, regc45: (u8, u16) ) -> Result<u16, Self::Error>

Read from the PHY Registers as Clause 45.

async fn write_cl22( &mut self, phy_id: u8, reg: u8, val: u16 ) -> Result<(), Self::Error>

Write to the PHY Registers as Clause 22.

async fn write_cl45( &mut self, phy_id: u8, regc45: (u8, u16), value: u16 ) -> AEResult<(), SPI::Error>

Write to the PHY Registers as Clause 45.

type Error = AdinError<<SPI as ErrorType>::Error>

Error type.