Struct ClockConfig

#[non_exhaustive]
pub struct ClockConfig {
    pub rosc: Option<RoscConfig>,
    pub xosc: Option<XoscConfig>,
    pub ref_clk: RefClkConfig,
    pub sys_clk: SysClkConfig,
    pub peri_clk_src: Option<PeriClkSrc>,
    pub usb_clk: Option<UsbClkConfig>,
    pub adc_clk: Option<AdcClkConfig>,
    pub rtc_clk: Option<RtcClkConfig>,
    pub core_voltage: CoreVoltage,
    pub voltage_stabilization_delay_us: Option<u32>,
}

CLock configuration.

Fields (Non-exhaustive)

Non-exhaustive structs could have additional fields added in future. Therefore, non-exhaustive structs cannot be constructed in external crates using the traditional Struct { .. } syntax; cannot be matched against without a wildcard ..; and struct update syntax will not work.

rosc: Option<RoscConfig>

Ring oscillator configuration.

xosc: Option<XoscConfig>

External oscillator configuration.

ref_clk: RefClkConfig

Reference clock configuration.

sys_clk: SysClkConfig

System clock configuration.

peri_clk_src: Option<PeriClkSrc>

Peripheral clock source configuration.

usb_clk: Option<UsbClkConfig>

USB clock configuration.

adc_clk: Option<AdcClkConfig>

ADC clock configuration.

rtc_clk: Option<RtcClkConfig>

RTC clock configuration.

core_voltage: CoreVoltage

Core voltage scaling. Defaults to 1.10V.

voltage_stabilization_delay_us: Option<u32>

Voltage stabilization delay in microseconds. If not set, defaults will be used based on voltage level.

Implementations

impl ClockConfig

pub fn crystal(crystal_hz: u32) -> Self

Clock configuration derived from external crystal.

This uses default settings for most parameters, suitable for typical use cases. For manual control of PLL parameters, use new_manual() or modify the struct fields directly.

pub fn rosc() -> Self

Clock configuration from internal oscillator.

pub fn system_freq(hz: u32) -> Result<Self, ClockError>

Configure clocks derived from an external crystal with specific system frequency.

This function calculates optimal PLL parameters to achieve the requested system frequency. This only works for the usual 12MHz crystal. In case a different crystal is used, You will have to set the PLL parameters manually.

Arguments

• sys_freq_hz - The desired system clock frequency in Hz

Returns

A ClockConfig configured to achieve the requested system frequency using the the usual 12Mhz crystal, or an error if no valid parameters can be found.

Note on core voltage:

For RP2040: To date the only officially documented core voltages (see Datasheet section 2.15.3.1. Instances) are:

• Up to 133MHz: V1_10 (default)
• Above 133MHz: V1_15, but in the context of the datasheet covering reaching up to 200Mhz That way all other frequencies below 133MHz or above 200MHz are not explicitly documented and not covered here. In case You want to go below 133MHz or above 200MHz and want a different voltage, You will have to set that manually and with caution.

For RP235x: At this point in time there is no official manufacturer endorsement for running the chip on other core voltages and/or other clock speeds than the defaults. Using this function is experimental and may not work as expected or even damage the chip.

Returns

A Result containing either the configured ClockConfig or a ClockError.

pub fn manual_pll( xosc_hz: u32, pll_config: PllConfig, core_voltage: CoreVoltage, ) -> Self

Configure with manual PLL settings for full control over system clock

This method provides a simple way to configure the system with custom PLL parameters without needing to understand the full nested configuration structure.

Arguments

• xosc_hz - The frequency of the external crystal in Hz
• pll_config - The PLL configuration parameters to achieve desired frequency
• core_voltage - Voltage scaling for overclocking (required for >133MHz)

Returns

A ClockConfig configured with the specified PLL parameters

Example

// Configure for 200MHz operation
let config = Config::default();
config.clocks = ClockConfig::manual_pll(
    12_000_000,
    PllConfig {
        refdiv: 1,    // Reference divider (12 MHz / 1 = 12 MHz)
        fbdiv: 100,   // Feedback divider (12 MHz * 100 = 1200 MHz VCO)
        post_div1: 3, // First post divider (1200 MHz / 3 = 400 MHz)
        post_div2: 2, // Second post divider (400 MHz / 2 = 200 MHz)
    },
    CoreVoltage::V1_15
);

Trait Implementations

impl Default for ClockConfig

fn default() -> Self

Creates a minimal default configuration with safe values.

This configuration uses the ring oscillator (ROSC) as the clock source and sets minimal defaults that guarantee a working system. It’s intended as a starting point for manual configuration.

Most users should use one of the more specific configuration functions:

• ClockConfig::crystal() - Standard configuration with external crystal
• ClockConfig::rosc() - Configuration using only the internal oscillator
• ClockConfig::system_freq() - Configuration for a specific system frequency