Struct StateMachineTx 

pub struct StateMachineTx<'d, PIO: Instance, const SM: usize> { /* private fields */ }

Type representing a state machine TX FIFO.

Implementations

impl<'d, PIO: Instance, const SM: usize> StateMachineTx<'d, PIO, SM>

pub fn empty(&self) -> bool

Check if TX FIFO is empty.

pub fn full(&self) -> bool

Check if TX FIFO is full.

pub fn level(&self) -> u8

Check TX FIFO level.

pub fn stalled(&self) -> bool

Check if state machine has stalled on empty TX FIFO.

pub fn overflowed(&self) -> bool

Check if FIFO overflowed.

pub fn push(&mut self, v: u32)

Force push data to TX FIFO.

pub fn try_push(&mut self, v: u32) -> bool

Attempt to push data to TX FIFO.

pub fn wait_push<'a>(&'a mut self, value: u32) -> FifoOutFuture<'a, 'd, PIO, SM>

Wait until FIFO is ready for writing.

pub fn dreq(&self) -> TreqSel

Get the Data Request value for the TX FIFO.

This value can be used to configure DMA channel pacing.

pub fn fifo_address(&self) -> *mut u32

Get the address of the TX FIFO.

To manually read a word from the FIFO, use try_push or push.

pub fn dma_push<'a, W: Word>( &'a mut self, ch: &'a mut Channel<'_, Async>, data: &'a [W], bswap: bool, ) -> Transfer<'a>

Prepare a DMA transfer to TX FIFO.

pub fn dma_push_zeros<'a, W: Word>( &'a mut self, ch: &'a mut Channel<'_, Async>, len: usize, ) -> Transfer<'a>

Prepare a repeated DMA transfer to TX FIFO.