#[non_exhaustive]pub struct Config {
pub invert_a: bool,
pub invert_b: bool,
pub phase_correct: bool,
pub enable: bool,
pub divider_x16: u16,
pub compare_a: u16,
pub compare_b: u16,
pub top: u16,
}Expand description
The configuration of a PWM slice.
Note the period in clock cycles of a slice can be computed as:
(top + 1) * (phase_correct ? 1 : 2) * divider
Fields (Non-exhaustive)§
This struct is marked as non-exhaustive
Struct { .. } syntax; cannot be matched against without a wildcard ..; and struct update syntax will not work.invert_a: boolInverts the PWM output signal on channel A.
invert_b: boolInverts the PWM output signal on channel B.
phase_correct: boolEnables phase-correct mode for PWM operation. In phase-correct mode, the PWM signal is generated in such a way that the pulse is always centered regardless of the duty cycle. The output frequency is halved when phase-correct mode is enabled.
enable: boolEnables the PWM slice, allowing it to generate an output.
divider_x16: u16A fractional clock divider, as a fixed-point number with 8 integer bits
and 4 fractional bits (the divider multiplied by 16). For example, 16
divides by 1, 40 divides by 2.5, and the maximum 0xFFF divides by 255.9375.
It allows precise control over the PWM output frequency by gating the
PWM counter increment. A higher value will result in a slower output frequency.
compare_a: u16The output on channel A goes high when compare_a is higher than the
counter. A compare of 0 will produce an always low output, while a
compare of top + 1 will produce an always high output.
compare_b: u16The output on channel B goes high when compare_b is higher than the
counter. A compare of 0 will produce an always low output, while a
compare of top + 1 will produce an always high output.
top: u16The point at which the counter wraps, representing the maximum possible
period. The counter will either wrap to 0 or reverse depending on the
setting of phase_correct.