Enum CoreVoltage

#[repr(u8)]
pub enum CoreVoltage {
    V0_55 = 0,
    V0_60 = 1,
    V0_65 = 2,
    V0_70 = 3,
    V0_75 = 4,
    V0_80 = 5,
    V0_85 = 6,
    V0_90 = 7,
    V0_95 = 8,
    V1_00 = 9,
    V1_05 = 10,
    V1_10 = 11,
    V1_15 = 12,
    V1_20 = 13,
    V1_25 = 14,
    V1_30 = 15,
}

Core voltage regulator settings.

The voltage regulator can be configured for different output voltages. Higher voltages allow for higher clock frequencies but increase power consumption and heat.

Note: The maximum voltage is 1.30V, unless unlocked by setting unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register. For lack of practical use at this point in time, this is not implemented here. So the maximum voltage in this enum is 1.30V for now.

Variants

V0_55 = 0

0.55V

V0_60 = 1

0.60V

V0_65 = 2

0.65V

V0_70 = 3

0.70V

V0_75 = 4

0.75V

V0_80 = 5

0.80V

V0_85 = 6

0.85V

V0_90 = 7

0.90V

V0_95 = 8

0.95V

V1_00 = 9

1.00V

V1_05 = 10

1.05V

V1_10 = 11

1.10V - Default voltage level

V1_15 = 12

1.15V

V1_20 = 13

1.20V

V1_25 = 14

1.25V

V1_30 = 15

1.30V

Trait Implementations

impl Clone for CoreVoltage

fn clone(&self) -> CoreVoltage

Returns a duplicate of the value.

const fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CoreVoltage

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Format for CoreVoltage

fn format(&self, f: Formatter<'_>)

Writes the defmt representation of self to fmt.

impl PartialEq for CoreVoltage

fn eq(&self, other: &CoreVoltage) -> bool

Tests for self and other values to be equal, and is used by ==.

const fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CoreVoltage

impl Eq for CoreVoltage

impl StructuralPartialEq for CoreVoltage