pub struct CcAes { /* private fields */ }
Expand description
CRYPTOCELL AES engine
Implementations§
Source§impl CcAes
impl CcAes
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
Sourcepub const fn aes_key_0(self, n: usize) -> Reg<u32, W>
pub const fn aes_key_0(self, n: usize) -> Reg<u32, W>
Description collection: AES key value to use. The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value.
Sourcepub const fn aes_iv_0(self, n: usize) -> Reg<u32, RW>
pub const fn aes_iv_0(self, n: usize) -> Reg<u32, RW>
Description collection: AES Initialization Vector (IV) to use. The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV.
Sourcepub const fn aes_ctr(self, n: usize) -> Reg<u32, RW>
pub const fn aes_ctr(self, n: usize) -> Reg<u32, RW>
Description collection: AES counter (CTR) to use. The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR.
Sourcepub const fn aes_sk(self) -> Reg<AesSk, W>
pub const fn aes_sk(self) -> Reg<AesSk, W>
Writing to this address trigger sampling of the HW key to the AES_KEY_0 register
Sourcepub const fn aes_cmac_init(self) -> Reg<AesCmacInit, W>
pub const fn aes_cmac_init(self) -> Reg<AesCmacInit, W>
Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations.
Sourcepub const fn aes_remaining_bytes(self) -> Reg<u32, RW>
pub const fn aes_remaining_bytes(self) -> Reg<u32, RW>
This register should be set with the amount of remaining bytes until the end of the current AES operation.
Sourcepub const fn aes_control(self) -> Reg<AesControl, RW>
pub const fn aes_control(self) -> Reg<AesControl, RW>
Control the AES engine behavior.
Sourcepub const fn aes_hw_flags(self) -> Reg<AesHwFlags, R>
pub const fn aes_hw_flags(self) -> Reg<AesHwFlags, R>
Hardware configuration of the AES engine. Reset value holds the supported features.
Sourcepub const fn aes_ctr_no_increment(self) -> Reg<AesCtrNoIncrement, RW>
pub const fn aes_ctr_no_increment(self) -> Reg<AesCtrNoIncrement, RW>
This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks
Sourcepub const fn aes_sw_reset(self) -> Reg<AesSwReset, W>
pub const fn aes_sw_reset(self) -> Reg<AesSwReset, W>
Reset the AES engine.
Sourcepub const fn aes_cmac_size0_kick(self) -> Reg<AesCmacSize0Kick, W>
pub const fn aes_cmac_size0_kick(self) -> Reg<AesCmacSize0Kick, W>
Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register.
Trait Implementations§
impl Copy for CcAes
impl Eq for CcAes
impl Send for CcAes
impl StructuralPartialEq for CcAes
impl Sync for CcAes
Auto Trait Implementations§
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
Source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)