Struct Etm

pub struct Etm { /* private fields */ }

Embedded Trace Macrocell

Implementations

impl Etm

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn trcprgctlr(self) -> Reg<Trcprgctlr, RW>

Enables the trace unit.

pub const fn trcprocselr(self) -> Reg<Trcprocselr, RW>

Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. Implemented if TRCIDR3.NUMPROC is greater than zero.

pub const fn trcstatr(self) -> Reg<Trcstatr, RW>

Idle status bit

pub const fn trcconfigr(self) -> Reg<Trcconfigr, RW>

Controls the tracing options This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle.

pub const fn trceventctl0r(self) -> Reg<Trceventctl0r, RW>

Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN.

pub const fn trceventctl1r(self) -> Reg<Trceventctl1r, RW>

Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle.

pub const fn trcstallctlr(self) -> Reg<Trcstallctlr, RW>

Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1.

pub const fn trctsctlr(self) -> Reg<Trctsctlr, RW>

Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1.

pub const fn trcsyncpr(self) -> Reg<Trcsyncpr, RW>

Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or not idle. If writes are permitted then the register must be programmed.

pub const fn trcccctlr(self) -> Reg<Trcccctlr, RW>

Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.CCI==1.

pub const fn trcbbctlr(self) -> Reg<Trcbbctlr, RW>

Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1.

pub const fn trctraceidr(self) -> Reg<Trctraceidr, RW>

Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle.

pub const fn trcqctlr(self) -> Reg<Trcqctlr, RW>

Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00.

pub const fn trcvictlr(self) -> Reg<Trcvictlr, RW>

Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic.

pub const fn trcviiectlr(self) -> Reg<Trcviiectlr, RW>

ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented.

pub const fn trcvissctlr(self) -> Reg<Trcvissctlr, RW>

Use this to set, or read, the single address comparators that control the ViewInst start/stop logic. The start/stop logic is active for an instruction which causes a start and remains active up to and including an instruction which causes a stop, and then the start/stop logic becomes inactive. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed.

pub const fn trcvipcssctlr(self) -> Reg<Trcvipcssctlr, RW>

Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed.

pub const fn trcvdctlr(self) -> Reg<Trcvdctlr, RW>

Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1.

pub const fn trcvdsacctlr(self) -> Reg<Trcvdsacctlr, RW>

ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented.

pub const fn trcvdarcctlr(self) -> Reg<Trcvdarcctlr, RW>

ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented.

pub const fn trcseqevr(self, n: usize) -> Reg<Trcseqevr, RW>

Description collection: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

pub const fn trcseqrstevr(self) -> Reg<Trcseqrstevr, RW>

Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

pub const fn trcseqstr(self) -> Reg<Trcseqstr, RW>

Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

pub const fn trcextinselr(self) -> Reg<Trcextinselr, RW>

Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

pub const fn trccntrldvr(self, n: usize) -> Reg<Trccntrldvr, RW>

Description collection: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is enabled or not idle.

pub const fn trccntctlr(self, n: usize) -> Reg<Trccntctlr, RW>

Description collection: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle.

pub const fn trccntvr(self, n: usize) -> Reg<Trccntvr, RW>

Description collection: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If software uses counter n then it must write to this register to set the initial counter value. Might ignore writes when the trace unit is enabled or not idle.

pub const fn trcrsctlr(self, n: usize) -> Reg<Trcrsctlr, RW>

Description collection: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE behavior of the resource selector occurs, so the resource selector might fire unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.

pub const fn trcssccr0(self) -> Reg<Trcssccr0, RW>

Controls the single-shot comparator.

pub const fn trcsscsr0(self) -> Reg<Trcsscsr0, RW>

Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses.

pub const fn trcsspcicr0(self) -> Reg<Trcsspcicr0, RW>

Selects the processor comparator inputs for Single-shot control.

pub const fn trcpdcr(self) -> Reg<Trcpdcr, RW>

Controls the single-shot comparator.

pub const fn trcpdsr(self) -> Reg<Trcpdsr, RW>

Indicates the power down status of the ETM.

pub const fn trcitatbidr(self) -> Reg<Trcitatbidr, RW>

Sets the state of output pins.

pub const fn trcitiatbinr(self) -> Reg<Trcitiatbinr, RW>

Reads the state of the input pins.

pub const fn trcitiatboutr(self) -> Reg<Trcitiatboutr, RW>

Sets the state of the output pins.

pub const fn trcitctrl(self) -> Reg<Trcitctrl, RW>

Enables topology detection or integration testing, by putting ETM-M33 into integration mode.

pub const fn trcclaimset(self) -> Reg<Trcclaimset, RW>

Sets bits in the claim tag and determines the number of claim tag bits implemented.

pub const fn trcclaimclr(self) -> Reg<Trcclaimclr, RW>

Clears bits in the claim tag and determines the current value of the claim tag.

pub const fn trcauthstatus(self) -> Reg<Trcauthstatus, RW>

Indicates the current level of tracing permitted by the system

pub const fn trcdevarch(self) -> Reg<Trcdevarch, R>

The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component

pub const fn trcdevtype(self) -> Reg<Trcdevtype, R>

Controls the single-shot comparator.

pub const fn trcpidr(self, n: usize) -> Reg<u32, RW>

Description collection: Coresight peripheral identification registers.

pub const fn trccidr(self, n: usize) -> Reg<u32, RW>

Description collection: Coresight component identification registers.

Trait Implementations

impl Clone for Etm

fn clone(&self) -> Etm

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Etm

fn eq(&self, other: &Etm) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Etm

impl Eq for Etm

impl Send for Etm

impl StructuralPartialEq for Etm

impl Sync for Etm