Struct Tpiu

pub struct Tpiu { /* private fields */ }

Trace Port Interface Unit

Implementations

impl Tpiu

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn supportedportsizes(self) -> Reg<Supportedportsizes, RW>

Each bit location is a single port size that is supported on the device.

pub const fn currentportsize(self) -> Reg<Currentportsize, RW>

Each bit location is a single port size. One bit can be set, and indicates the current port size.

pub const fn supportedtriggermodes(self) -> Reg<Supportedtriggermodes, RW>

The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system.

pub const fn triggercountervalue(self) -> Reg<Triggercountervalue, RW>

The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices.

pub const fn triggermultiplier(self) -> Reg<Triggermultiplier, RW>

The Trigger_multiplier register contains the selectors for the trigger counter multiplier.

pub const fn suppportedtestpatternmodes( self, ) -> Reg<Suppportedtestpatternmodes, RW>

The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device.

pub const fn currenttestpatternmodes(self) -> Reg<Currenttestpatternmodes, RW>

Current_test_pattern_mode indicates the current test pattern or mode selected.

pub const fn tprcr(self) -> Reg<Tprcr, RW>

The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value.

pub const fn ffsr(self) -> Reg<Ffsr, RW>

The FFSR register indicates the current status of the formatter and flush features available in the TPIU.

pub const fn ffcr(self) -> Reg<Ffcr, RW>

The FFCR register controls the generation of stop, trigger, and flush events.

pub const fn fscr(self) -> Reg<Fscr, RW>

The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size.

pub const fn extctlinport(self) -> Reg<Extctlinport, RW>

Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution.

pub const fn extctloutport(self) -> Reg<Extctloutport, RW>

Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins.

pub const fn ittrflinack(self) -> Reg<Ittrflinack, RW>

The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU.

pub const fn ittrflin(self) -> Reg<Ittrflin, RW>

The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU.

pub const fn itatbdata0(self) -> Reg<Itatbdata0, RW>

The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH.

pub const fn itatbctr2(self) -> Reg<Itatbctr2, RW>

Enables control of the atreadys and afvalids outputs of the TPIU.

pub const fn itatbctr1(self) -> Reg<Itatbctr1, RW>

The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH.

pub const fn itatbctr0(self) -> Reg<Itatbctr0, RW>

The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH.

pub const fn itctrl(self) -> Reg<Itctrl, RW>

Used to enable topology detection. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving.

pub const fn claimset(self) -> Reg<Claimset, RW>

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented.

pub const fn claimclr(self) -> Reg<Claimclr, RW>

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag.

pub const fn lar(self) -> Reg<Lar, RW>

This is used to enable write access to device registers.

pub const fn lsr(self) -> Reg<Lsr, RW>

This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register.

pub const fn authstatus(self) -> Reg<Authstatus, RW>

Indicates the current level of tracing permitted by the system

pub const fn devid(self) -> Reg<Devid, R>

Indicates the capabilities of the component.

pub const fn devtype(self) -> Reg<Devtype, R>

The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.

pub const fn pidr4(self) -> Reg<u32, RW>

Coresight peripheral identification registers.

pub const fn pidr_0(self) -> Reg<u32, RW>

Coresight peripheral identification registers.

pub const fn pidr_1(self) -> Reg<u32, RW>

Coresight peripheral identification registers.

pub const fn pidr_2(self) -> Reg<u32, RW>

Coresight peripheral identification registers.

pub const fn pidr_3(self) -> Reg<u32, RW>

Coresight peripheral identification registers.

pub const fn cidr_0(self) -> Reg<u32, RW>

Coresight component identification registers.

pub const fn cidr_1(self) -> Reg<u32, RW>

Coresight component identification registers.

pub const fn cidr_2(self) -> Reg<u32, RW>

Coresight component identification registers.

pub const fn cidr_3(self) -> Reg<u32, RW>

Coresight component identification registers.

Trait Implementations

impl Clone for Tpiu

fn clone(&self) -> Tpiu

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Tpiu

fn eq(&self, other: &Tpiu) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Tpiu

impl Eq for Tpiu

impl Send for Tpiu

impl StructuralPartialEq for Tpiu

impl Sync for Tpiu