Struct Dma

pub struct Dma(pub *mut u8);

DMA with separate read and write masters

Tuple Fields

0: *mut u8

Implementations

impl Dma

pub fn ch(self, n: usize) -> Channel

pub fn intr(self) -> Reg<Intr, RW>

Interrupt Status (raw)

pub fn inte0(self) -> Reg<Inte0, RW>

Interrupt Enables for IRQ 0

pub fn intf0(self) -> Reg<Intf0, RW>

Force Interrupts

pub fn ints0(self) -> Reg<Ints0, RW>

Interrupt Status for IRQ 0

pub fn inte1(self) -> Reg<Inte1, RW>

Interrupt Enables for IRQ 1

pub fn intf1(self) -> Reg<Intf1, RW>

Force Interrupts for IRQ 1

pub fn ints1(self) -> Reg<Ints1, RW>

Interrupt Status (masked) for IRQ 1

pub fn timer(self, n: usize) -> Reg<Timer, RW>

Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

pub fn multi_chan_trigger(self) -> Reg<MultiChanTrigger, RW>

Trigger one or more channels simultaneously

pub fn sniff_ctrl(self) -> Reg<SniffCtrl, RW>

Sniffer Control

pub fn sniff_data(self) -> Reg<u32, RW>

Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.

pub fn fifo_levels(self) -> Reg<FifoLevels, RW>

Debug RAF, WAF, TDF levels

pub fn chan_abort(self) -> Reg<ChanAbort, RW>

Abort an in-progress transfer sequence on one or more channels

pub fn n_channels(self) -> Reg<Nchannels, RW>

The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

Trait Implementations

impl Clone for Dma

fn clone(&self) -> Dma

Returns a duplicate of the value.

const fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Dma

fn eq(&self, other: &Dma) -> bool

Tests for self and other values to be equal, and is used by ==.

const fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Dma

impl Eq for Dma

impl Send for Dma

impl StructuralPartialEq for Dma

impl Sync for Dma