rp-pac

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rp2040

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Module rp_pac::adc::regs

source ·

Structs§

  • ADC Control and Status
  • Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256
  • FIFO control and status
  • Conversion result FIFO
  • Interrupt Enable
  • Result of most recent ADC conversion