Expand description
§rp-pac
This is a Peripheral Access Crate for Raspberry Pi Silicon microcontrollers.
This crate has been automatically generated from the SVD files in pico-sdk, using chiptool. Fixes are added to the SVD file to make the crate more amenable to writing HALs with, such as converting sets of identical registers/fields to arrays, merging identical registers and enums, etc.
This crate is used for the embassy-rp Rust Hardware Abstraction Layer (HAL) for the RPxxx microcontrollers.
§Supported chips
§License
The contents of this crate are auto-generated and licensed under the same terms as the underlying SVD file, which is licensed by Raspberry Pi Trading Ltd under a BSD-3-Clause licence.
Modules§
Enums§
Constants§
- Hardware access control registers
- Control and data interface to SAR ADC
- Additional registers mapped adjacent to the bootram, for use by the bootrom.
- Register block for busfabric control signals and performance counters
- Coresight block - RP specific registers
- DMA with separate read and write masters
- Cortex-M33 EPPB vendor register block for RP2350
- Glitch detector controls
- Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block.
- FIFO status and write access for HSTX
- DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are fixed values, set at hardware design time): IC_ULTRA_FAST_MODE ……………. 0x0 IC_UFM_TBUF_CNT_DEFAULT ……….. 0x8 IC_UFM_SCL_LOW_COUNT ………….. 0x0008 IC_UFM_SCL_HIGH_COUNT …………. 0x0006 IC_TX_TL …………………….. 0x0 IC_TX_CMD_BLOCK ………………. 0x1 IC_HAS_DMA …………………… 0x1 IC_HAS_ASYNC_FIFO …………….. 0x0 IC_SMBUS_ARP …………………. 0x0 IC_FIRST_DATA_BYTE_STATUS ……… 0x1 IC_INTR_IO …………………… 0x1 IC_MASTER_MODE ……………….. 0x1 IC_DEFAULT_ACK_GENERAL_CALL ……. 0x1 IC_INTR_POL ………………….. 0x1 IC_OPTIONAL_SAR ………………. 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ……… 0x055 IC_DEFAULT_SLAVE_ADDR …………. 0x055 IC_DEFAULT_HS_SPKLEN ………….. 0x1 IC_FS_SCL_HIGH_COUNT ………….. 0x0006 IC_HS_SCL_LOW_COUNT …………… 0x0008 IC_DEVICE_ID_VALUE ……………. 0x0 IC_10BITADDR_MASTER …………… 0x0 IC_CLK_FREQ_OPTIMIZATION ………. 0x0 IC_DEFAULT_FS_SPKLEN ………….. 0x7 IC_ADD_ENCODED_PARAMS …………. 0x0 IC_DEFAULT_SDA_HOLD …………… 0x000001 IC_DEFAULT_SDA_SETUP ………….. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ………………. 100 IC_EMPTYFIFO_HOLD_MASTER_EN ……. 1 IC_RESTART_EN ………………… 0x1 IC_TX_CMD_BLOCK_DEFAULT ……….. 0x0 IC_BUS_CLEAR_FEATURE ………….. 0x0 IC_CAP_LOADING ……………….. 100 IC_FS_SCL_LOW_COUNT …………… 0x000d APB_DATA_WIDTH ……………….. 32 IC_SDA_STUCK_TIMEOUT_DEFAULT …… 0xffffffff IC_SLV_DATA_NACK_ONLY …………. 0x1 IC_10BITADDR_SLAVE ……………. 0x0 IC_CLK_TYPE ………………….. 0x0 IC_SMBUS_UDID_MSB …………….. 0x0 IC_SMBUS_SUSPEND_ALERT ………… 0x0 IC_HS_SCL_HIGH_COUNT ………….. 0x0006 IC_SLV_RESTART_DET_EN …………. 0x1 IC_SMBUS …………………….. 0x0 IC_OPTIONAL_SAR_DEFAULT ……….. 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT …. 0x0 IC_USE_COUNTS ………………… 0x0 IC_RX_BUFFER_DEPTH ……………. 16 IC_SCL_STUCK_TIMEOUT_DEFAULT …… 0xffffffff IC_RX_FULL_HLD_BUS_EN …………. 0x1 IC_SLAVE_DISABLE ……………… 0x1 IC_RX_TL …………………….. 0x0 IC_DEVICE_ID …………………. 0x0 IC_HC_COUNT_VALUES ……………. 0x0 I2C_DYNAMIC_TAR_UPDATE ………… 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ….. 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ….. 0xffffffff IC_HS_MASTER_CODE …………….. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ….. 0xffff IC_SMBUS_UDID_LSB_DEFAULT ……… 0xffffffff IC_SS_SCL_HIGH_COUNT ………….. 0x0028 IC_SS_SCL_LOW_COUNT …………… 0x002f IC_MAX_SPEED_MODE …………….. 0x2 IC_STAT_FOR_CLK_STRETCH ……….. 0x0 IC_STOP_DET_IF_MASTER_ACTIVE …… 0x0 IC_DEFAULT_UFM_SPKLEN …………. 0x1 IC_TX_BUFFER_DEPTH ……………. 16
- SNPS OTP control IF (SBPI and RPi wrapper control)
- Predefined OTP data layout for RP2350
- Predefined OTP data layout for RP2350
- Programmable IO block
- Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use
- Simple PWM
- QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device.
- SHA-256 hash function implementation
- Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access.
- Register block for various chip control signals
- For managing simulation testbenches
- Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing
- ARM TrustZone RNG register block
- USB FS/LS controller device registers
- DPRAM layout for USB device.
- Auxiliary DMA access to XIP FIFOs, via fast AHB bus access
- QSPI flash execute-in-place block
- Controls the crystal oscillator