Clock control, can be changed on-the-fly (except for auxsrc)
Clock divisor, can be changed on-the-fly
Clock control, can be changed on-the-fly (except for auxsrc)
Clock divisor, can be changed on-the-fly
Clock control, can be changed on-the-fly (except for auxsrc)
Clock divisor, can be changed on-the-fly
Clock control, can be changed on-the-fly (except for auxsrc)
Clock divisor, can be changed on-the-fly
Clock control, can be changed on-the-fly (except for auxsrc)
Clock divisor, can be changed on-the-fly
Clock control, can be changed on-the-fly (except for auxsrc)
Clock divisor, can be changed on-the-fly
Clock control, can be changed on-the-fly (except for auxsrc)
Clock divisor, can be changed on-the-fly
indicates the state of the clock enable
indicates the state of the clock enable
Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period
The test interval is 0.98us * 2interval, but let’s call it 1us * 2interval The default gives a test interval of 250us
Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
Reference clock frequency in kHz
Result of frequency measurement, only valid when status_done=1
Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count
Frequency counter status
Interrupt Force
enable clock in sleep mode
enable clock in sleep mode
enable clock in wake mode
enable clock in wake mode