rp-pac

Crates

git

Versions

rp2040

Flavors

Module rp_pac::dma::regs

source ·

Structs§

  • Abort an in-progress transfer sequence on one or more channels
  • DMA Channel 5 Control and Status
  • Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
  • Debug RAF, WAF, TDF levels
  • Trigger one or more channels simultaneously
  • The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
  • Sniffer Control
  • Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.