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rp-pac

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git

Versions

rp235x

Flavors

rp_pac::pll

Module regs

Source

Structsยง

  • Cs
    Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz
  • FbdivInt
    Feedback divisor (note: this PLL does not support fractional division)
  • Inte
    Interrupt Enable
  • Intf
    Interrupt Force
  • Intr
    Raw Interrupts
  • Ints
    Interrupt status after masking & forcing
  • Prim
    Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2
  • Pwr
    Controls the PLL power modes.