Device address and endpoint control
Interrupt endpoint 8. Only valid for HOST mode.
Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.
Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.
Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn’t idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable.
Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in EP_ABORT_DONE is set when it is safe to modify the buffer control register.
Device only: Used in conjunction with EP_ABORT. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.
RX error count for each endpoint. Write to each field to reset the counter to 0.
Device: this bit must be set in conjunction with the STALL bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.
Device: bits are set when the IRQ_ON_NAK or IRQ_ON_STALL bits are set. For EP0 this comes from SIE_CTRL. For all other endpoints it comes from the endpoint control register.
TX error count for each endpoint. Write to each field to reset the counter to 0.
Interrupt Enable
interrupt endpoint control register
Used for debug only.
Main control register
Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.
SIE control register
SIE status register
Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.
Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred.
Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events.
Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.
Where to connect the USB controller. Should be to_phy by default.
Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.
This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.
Override enable for each control in usbphy_direct
Used to adjust trim values of USB phy pull down resistors.