Struct stm32_metapac::rcc::regs::Cfgr

#[repr(transparent)]
pub struct Cfgr(pub u32);

Expand description

RCC clock configuration register

Tuple Fields§

§0: u32

Implementations§

§

impl Cfgr

pub const fn sw(&self) -> Sw

System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.

pub fn set_sw(&mut self, val: Sw)

System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.

pub const fn sws(&self) -> Sw

System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved

pub fn set_sws(&mut self, val: Sw)

System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved

pub const fn hpre(&self) -> Hpre

AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1

pub fn set_hpre(&mut self, val: Hpre)

AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1

pub const fn ppre(&self) -> Ppre

APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1

pub fn set_ppre(&mut self, val: Ppre)

APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1

pub const fn mco2sel(&self) -> Mcosel

Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.

pub fn set_mco2sel(&mut self, val: Mcosel)

Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.

pub const fn mco2pre(&self) -> Mcopre

Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: … It is highly recommended to set this field before the MCO2 output is enabled.

pub fn set_mco2pre(&mut self, val: Mcopre)

Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: … It is highly recommended to set this field before the MCO2 output is enabled.

pub const fn mco1sel(&self) -> Mcosel

Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO.

pub fn set_mco1sel(&mut self, val: Mcosel)

Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO.

pub const fn mco1pre(&self) -> Mcopre

Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: … It is highly recommended to set this field before the MCO output is enabled.

pub fn set_mco1pre(&mut self, val: Mcopre)

Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: … It is highly recommended to set this field before the MCO output is enabled.