Struct stm32_metapac::rcc::regs::Cfgr

#[repr(transparent)]
pub struct Cfgr(pub u32);

Clock configuration register (RCC_CFGR)

Tuple Fields

0: u32

Implementations

impl Cfgr

pub const fn sw(&self) -> Sw

System clock Switch

pub fn set_sw(&mut self, val: Sw)

System clock Switch

pub const fn sws(&self) -> Sw

System Clock Switch Status

pub fn set_sws(&mut self, val: Sw)

System Clock Switch Status

pub const fn hpre(&self) -> Hpre

AHB prescaler

pub fn set_hpre(&mut self, val: Hpre)

AHB prescaler

pub const fn ppre1(&self) -> Ppre

APB Low speed prescaler (APB1)

pub fn set_ppre1(&mut self, val: Ppre)

APB Low speed prescaler (APB1)

pub const fn ppre2(&self) -> Ppre

APB high speed prescaler (APB2)

pub fn set_ppre2(&mut self, val: Ppre)

APB high speed prescaler (APB2)

pub const fn adcpre(&self) -> Adcpre

ADC prescaler

pub fn set_adcpre(&mut self, val: Adcpre)

ADC prescaler

pub const fn pllsrc(&self) -> Pllsrc

PLL entry clock source

pub fn set_pllsrc(&mut self, val: Pllsrc)

PLL entry clock source

pub const fn pllxtpre(&self) -> Pllxtpre

HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products.

pub fn set_pllxtpre(&mut self, val: Pllxtpre)

HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products.

pub const fn pllmul(&self) -> Pllmul

PLL Multiplication Factor

pub fn set_pllmul(&mut self, val: Pllmul)

PLL Multiplication Factor

pub const fn usbpre(&self) -> Usbpre

USB prescaler

pub fn set_usbpre(&mut self, val: Usbpre)

USB prescaler

pub const fn i2ssrc(&self) -> Issrc

I2S external clock source selection

pub fn set_i2ssrc(&mut self, val: Issrc)

I2S external clock source selection

pub const fn mcosel(&self) -> Mcosel

Microcontroller clock output

pub fn set_mcosel(&mut self, val: Mcosel)

Microcontroller clock output

pub const fn mcopre(&self) -> Mcopre

Microcontroller Clock Output Prescaler

pub fn set_mcopre(&mut self, val: Mcopre)

Microcontroller Clock Output Prescaler

pub const fn pllmcodiv(&self) -> Pllmcodiv

Do not divide PLL to MCO

pub fn set_pllmcodiv(&mut self, val: Pllmcodiv)

Do not divide PLL to MCO

Trait Implementations

impl Clone for Cfgr

fn clone(&self) -> Cfgr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cfgr

fn default() -> Cfgr

Returns the “default value” for a type.

impl PartialEq for Cfgr

fn eq(&self, other: &Cfgr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cfgr

impl Eq for Cfgr

impl StructuralPartialEq for Cfgr