Struct stm32_metapac::syscfg::regs::Cfgr1

#[repr(transparent)]
pub struct Cfgr1(pub u32);

configuration register 1

Tuple Fields

0: u32

Implementations

impl Cfgr1

pub const fn mem_mode(&self) -> MemMode

Memory mapping selection bits

pub fn set_mem_mode(&mut self, val: MemMode)

Memory mapping selection bits

pub const fn usb_it_rmp(&self) -> bool

USB interrupt remap 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively 1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively

pub fn set_usb_it_rmp(&mut self, val: bool)

USB interrupt remap 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively 1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively

pub const fn tim1_itr3_rmp(&self) -> bool

Timer 1 ITR3 selection 0: Not remapped 1: TIM1_ITR3 = TIM17_OC

pub fn set_tim1_itr3_rmp(&mut self, val: bool)

Timer 1 ITR3 selection 0: Not remapped 1: TIM1_ITR3 = TIM17_OC

pub const fn dac1_trig_rmp(&self) -> bool

DAC trigger remap (when TSEL = 001) 0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices 1: DAC trigger is TIM3_TRGO

pub fn set_dac1_trig_rmp(&mut self, val: bool)

DAC trigger remap (when TSEL = 001) 0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices 1: DAC trigger is TIM3_TRGO

pub const fn dac_trig_rmp(&self) -> bool

DAC trigger remap (when TSEL = 001) 0: Not remapped 1: DAC trigger is TIM3_TRGO

pub fn set_dac_trig_rmp(&mut self, val: bool)

DAC trigger remap (when TSEL = 001) 0: Not remapped 1: DAC trigger is TIM3_TRGO

pub const fn adc2_dma_rmp(&self) -> bool

ADC24 DMA remapping bit 0: ADC24 DMA requests mapped on DMA2 channels 1 and 2 1: ADC24 DMA requests mapped on DMA2 channels 3 and 4

pub fn set_adc2_dma_rmp(&mut self, val: bool)

ADC24 DMA remapping bit 0: ADC24 DMA requests mapped on DMA2 channels 1 and 2 1: ADC24 DMA requests mapped on DMA2 channels 3 and 4

pub const fn tim16_dma_rmp(&self) -> bool

TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4

pub fn set_tim16_dma_rmp(&mut self, val: bool)

TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4

pub const fn tim17_dma_rmp(&self) -> bool

TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2

pub fn set_tim17_dma_rmp(&mut self, val: bool)

TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2

pub const fn tim6_dac1_ch1_dma_rmp(&self) -> bool

TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3

pub fn set_tim6_dac1_ch1_dma_rmp(&mut self, val: bool)

TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3

pub const fn tim6_dac1_dma_rmp(&self) -> bool

TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3

pub fn set_tim6_dac1_dma_rmp(&mut self, val: bool)

TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3

pub const fn tim6_dac1_out1_dma_rmp(&self) -> bool

TIM6 and DAC1 DMA request remapping bit 0: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 1: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3

pub fn set_tim6_dac1_out1_dma_rmp(&mut self, val: bool)

TIM6 and DAC1 DMA request remapping bit 0: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 1: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3

pub const fn tim7_dac1_ch2_dma_rmp(&self) -> bool

TIM7 and DAC2 DMA request remapping bit 0: Not remapped 1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4

pub fn set_tim7_dac1_ch2_dma_rmp(&mut self, val: bool)

TIM7 and DAC2 DMA request remapping bit 0: Not remapped 1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4

pub const fn tim7_dac1_out2_dma_rmp(&self) -> bool

TIM7 and DAC2 DMA request remapping bit 0: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 1: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4

pub fn set_tim7_dac1_out2_dma_rmp(&mut self, val: bool)

TIM7 and DAC2 DMA request remapping bit 0: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 1: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4

pub const fn dac2_ch1_dma_rmp(&self) -> bool

DAC2 channel1 DMA remap 0: Not remapped 1: DAC2_CH1 DMA requests mapped on DMA1 channel 5

pub fn set_dac2_ch1_dma_rmp(&mut self, val: bool)

DAC2 channel1 DMA remap 0: Not remapped 1: DAC2_CH1 DMA requests mapped on DMA1 channel 5

pub const fn tim18_dac2_out1_dma_rmp(&self) -> bool

TIM18 and DAC2_OUT1 DMA request remapping bit 0: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 1: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5

pub fn set_tim18_dac2_out1_dma_rmp(&mut self, val: bool)

TIM18 and DAC2_OUT1 DMA request remapping bit 0: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 1: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5

pub const fn i2c_pb6_fmp(&self) -> Fmp

Fast Mode Plus (FM+) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed

pub fn set_i2c_pb6_fmp(&mut self, val: Fmp)

Fast Mode Plus (FM+) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed

pub const fn i2c_pb7_fmp(&self) -> Fmp

Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed

pub fn set_i2c_pb7_fmp(&mut self, val: Fmp)

Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed

pub const fn i2c_pb8_fmp(&self) -> Fmp

Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed

pub fn set_i2c_pb8_fmp(&mut self, val: Fmp)

Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed

pub const fn i2c_pb9_fmp(&self) -> Fmp

Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed

pub fn set_i2c_pb9_fmp(&mut self, val: Fmp)

Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed

pub const fn i2c1_fmp(&self) -> Fmp

I2C1 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits

pub fn set_i2c1_fmp(&mut self, val: Fmp)

I2C1 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits

pub const fn i2c2_fmp(&self) -> Fmp

I2C2 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits

pub fn set_i2c2_fmp(&mut self, val: Fmp)

I2C2 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits

pub const fn encoder_mode(&self) -> EncoderMode

Encoder mode

pub fn set_encoder_mode(&mut self, val: EncoderMode)

Encoder mode

pub const fn i2c3_fmp(&self) -> Fmp

I2C3 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits

pub fn set_i2c3_fmp(&mut self, val: Fmp)

I2C3 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits

pub const fn vbat_mon(&self) -> bool

Enable the power switch to deliver VBAT voltage on ADC channel 18 input

pub fn set_vbat_mon(&mut self, val: bool)

Enable the power switch to deliver VBAT voltage on ADC channel 18 input

pub const fn fpu_ie(&self, n: usize) -> bool

Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable

pub fn set_fpu_ie(&mut self, n: usize, val: bool)

Idx 0: Invalid operation interrupt enable; Idx 1: Devide-by-zero interrupt enable; Idx 2: Underflow interrupt enable; Idx 3: Overflow interrupt enable; Idx 4: Input denormal interrupt enable; Idx 5: Inexact interrupt enable

Trait Implementations

impl Clone for Cfgr1

fn clone(&self) -> Cfgr1

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cfgr1

fn default() -> Cfgr1

Returns the “default value” for a type.

impl PartialEq for Cfgr1

fn eq(&self, other: &Cfgr1) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cfgr1

impl Eq for Cfgr1

impl StructuralEq for Cfgr1

impl StructuralPartialEq for Cfgr1