Struct Icr

#[repr(transparent)]
pub struct Icr(pub u32);

Tuple Fields§

§0: u32

Implementations§

§

impl Icr

pub const fn clrjovrf(&self) -> bool

Clear the injected conversion overrun flag.

pub const fn set_clrjovrf(&mut self, val: bool)

Clear the injected conversion overrun flag.

pub const fn clrrovrf(&self) -> bool

Clear the regular conversion overrun flag.

pub const fn set_clrrovrf(&mut self, val: bool)

Clear the regular conversion overrun flag.

pub const fn clrckabf(&self) -> u8

Clear the clock absence flag CLRCKABF[y]=0: Writing ‘0’ has no effect CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

pub const fn set_clrckabf(&mut self, val: u8)

Clear the clock absence flag CLRCKABF[y]=0: Writing ‘0’ has no effect CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y]. Note: CLRCKABF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

pub const fn clrscdf(&self) -> u8

Clear the short-circuit detector flag CLRSCDF[y]=0: Writing ‘0’ has no effect CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).

pub const fn set_clrscdf(&mut self, val: u8)

Clear the short-circuit detector flag CLRSCDF[y]=0: Writing ‘0’ has no effect CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the DFSDM_FLTxISR register Note: CLRSCDF[7:0] is present only in DFSDM_FLT0ICR register (filter x=0).