Struct stm32_metapac::dsihost::regs::Wpcr0

#[repr(transparent)]
pub struct Wpcr0(pub u32);

DSI Wrapper PHY Configuration Register 0.

Tuple Fields

0: u32

Implementations

impl Wpcr0

pub const fn uix4(&self) -> u8

Unit Interval multiplied by 4.

pub fn set_uix4(&mut self, val: u8)

Unit Interval multiplied by 4.

pub const fn swcl(&self) -> bool

Swap Clock Lane pins.

pub fn set_swcl(&mut self, val: bool)

Swap Clock Lane pins.

pub const fn swdl0(&self) -> bool

Swap Data Lane 0 pins.

pub fn set_swdl0(&mut self, val: bool)

Swap Data Lane 0 pins.

pub const fn swdl1(&self) -> bool

Swap Data Lane 1 pins.

pub fn set_swdl1(&mut self, val: bool)

Swap Data Lane 1 pins.

pub const fn hsicl(&self) -> bool

Invert Hight-Speed data signal on Clock Lane.

pub fn set_hsicl(&mut self, val: bool)

Invert Hight-Speed data signal on Clock Lane.

pub const fn hsidl0(&self) -> bool

Invert the Hight-Speed data signal on Data Lane 0.

pub fn set_hsidl0(&mut self, val: bool)

Invert the Hight-Speed data signal on Data Lane 0.

pub const fn hsidl1(&self) -> bool

Invert the High-Speed data signal on Data Lane 1.

pub fn set_hsidl1(&mut self, val: bool)

Invert the High-Speed data signal on Data Lane 1.

pub const fn ftxsmcl(&self) -> bool

Force in TX Stop Mode the Clock Lane.

pub fn set_ftxsmcl(&mut self, val: bool)

Force in TX Stop Mode the Clock Lane.

pub const fn ftxsmdl(&self) -> bool

Force in TX Stop Mode the Data Lanes.

pub fn set_ftxsmdl(&mut self, val: bool)

Force in TX Stop Mode the Data Lanes.

pub const fn cdoffdl(&self) -> bool

Contention Detection OFF on Data Lanes.

pub fn set_cdoffdl(&mut self, val: bool)

Contention Detection OFF on Data Lanes.

pub const fn tddl(&self) -> bool

Turn Disable Data Lanes.

pub fn set_tddl(&mut self, val: bool)

Turn Disable Data Lanes.

pub const fn pden(&self) -> bool

Pull-Down Enable.

pub fn set_pden(&mut self, val: bool)

Pull-Down Enable.

pub const fn tclkprepen(&self) -> bool

custom time for tCLK-PREPARE Enable.

pub fn set_tclkprepen(&mut self, val: bool)

custom time for tCLK-PREPARE Enable.

pub const fn tclkzeroen(&self) -> bool

custom time for tCLK-ZERO Enable.

pub fn set_tclkzeroen(&mut self, val: bool)

custom time for tCLK-ZERO Enable.

pub const fn thsprepen(&self) -> bool

custom time for tHS-PREPARE Enable.

pub fn set_thsprepen(&mut self, val: bool)

custom time for tHS-PREPARE Enable.

pub const fn thstrailen(&self) -> bool

custom time for tHS-TRAIL Enable.

pub fn set_thstrailen(&mut self, val: bool)

custom time for tHS-TRAIL Enable.

pub const fn thszeroen(&self) -> bool

custom time for tHS-ZERO Enable.

pub fn set_thszeroen(&mut self, val: bool)

custom time for tHS-ZERO Enable.

pub const fn tlpxden(&self) -> bool

custom time for tLPX for Data lanes Enable.

pub fn set_tlpxden(&mut self, val: bool)

custom time for tLPX for Data lanes Enable.

pub const fn thsexiten(&self) -> bool

custom time for tHS-EXIT Enable.

pub fn set_thsexiten(&mut self, val: bool)

custom time for tHS-EXIT Enable.

pub const fn tlpxcen(&self) -> bool

custom time for tLPX for Clock lane Enable.

pub fn set_tlpxcen(&mut self, val: bool)

custom time for tLPX for Clock lane Enable.

pub const fn tclkposten(&self) -> bool

custom time for tCLK-POST Enable.

pub fn set_tclkposten(&mut self, val: bool)

custom time for tCLK-POST Enable.

Trait Implementations

impl Clone for Wpcr0

fn clone(&self) -> Wpcr0

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Wpcr0

fn default() -> Wpcr0

Returns the “default value” for a type.

impl PartialEq for Wpcr0

fn eq(&self, other: &Wpcr0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Wpcr0

impl Eq for Wpcr0

impl StructuralPartialEq for Wpcr0