Struct stm32_metapac::ucpd::regs::Cr

#[repr(transparent)]
pub struct Cr(pub u32);

Expand description

control register

Tuple Fields§

§0: u32

Implementations§

§

impl Cr

pub const fn txmode(&self) -> Txmode

Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the “tBISTContMode” delay), disable the peripheral (UCPDEN = 0).

pub fn set_txmode(&mut self, val: Txmode)

Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the “tBISTContMode” delay), disable the peripheral (UCPDEN = 0).

pub const fn txsend(&self) -> bool

Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded.

pub fn set_txsend(&mut self, val: bool)

Command to send a Tx packet The bit is cleared by hardware as soon as the packet transmission begins or is discarded.

pub const fn txhrst(&self) -> bool

Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded.

pub fn set_txhrst(&mut self, val: bool)

Command to send a Tx Hard Reset The bit is cleared by hardware as soon as the message transmission begins or is discarded.

pub const fn rxmode(&self) -> bool

Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message.

pub fn set_rxmode(&mut self, val: bool)

Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message.

pub const fn phyrxen(&self) -> bool

USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set.

pub fn set_phyrxen(&mut self, val: bool)

USB Power Delivery receiver enable Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set.

pub const fn phyccsel(&self) -> Phyccsel

CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach.

pub fn set_phyccsel(&mut self, val: Phyccsel)

CC1/CC2 line selector for USB Power Delivery signaling The selection depends on the cable orientation as discovered at attach.

pub const fn anasubmode(&self) -> u8

Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield.

pub fn set_anasubmode(&mut self, val: u8)

Analog PHY sub-mode Refer to TYPEC_VSTATE_CCx for the effect of this bitfield.

pub const fn anamode(&self) -> Anamode

Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0].

pub fn set_anamode(&mut self, val: Anamode)

Analog PHY operating mode The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0].

pub const fn ccenable(&self) -> Ccenable

CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source.

pub fn set_ccenable(&mut self, val: Ccenable)

CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source.

pub const fn cc1vconnen(&self) -> bool

VCONN switch enable for CC1

pub fn set_cc1vconnen(&mut self, val: bool)

VCONN switch enable for CC1

pub const fn cc2vconnen(&self) -> bool

VCONN switch enable for CC2

pub fn set_cc2vconnen(&mut self, val: bool)

VCONN switch enable for CC2

pub const fn dbatten(&self) -> bool

Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured.

pub fn set_dbatten(&mut self, val: bool)

Dead battery function enable The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register. Dead battery function only operates if the external circuit is appropriately configured.

pub const fn frsrxen(&self) -> bool

FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink.

pub fn set_frsrxen(&mut self, val: bool)

FRS event detection enable Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable Clear the bit when the device is attached to an FRS-incapable source/sink.

pub const fn frstx(&self) -> bool

FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0.

pub fn set_frstx(&mut self, val: bool)

FRS Tx signaling enable. Setting the bit enables FRS Tx signaling. The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0.

pub const fn rdch(&self) -> bool

Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to “USB Type-C ECN for Source VCONN Discharge”. The CCENABLE[1:0] bitfield must be set accordingly, too.

pub fn set_rdch(&mut self, val: bool)

Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to “USB Type-C ECN for Source VCONN Discharge”. The CCENABLE[1:0] bitfield must be set accordingly, too.

pub const fn cc1tcdis(&self) -> bool

CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0].

pub fn set_cc1tcdis(&mut self, val: bool)

CC1 Type-C detector disable The bit disables the Type-C detector on the CC1 line. When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0].

pub const fn cc2tcdis(&self) -> bool

CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0].

pub fn set_cc2tcdis(&mut self, val: bool)

CC2 Type-C detector disable The bit disables the Type-C detector on the CC2 line. When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0].