Struct stm32_metapac::adc::regs::Isr

#[repr(transparent)]
pub struct Isr(pub u32);

interrupt and status register

Tuple Fields

0: u32

Implementations

impl Isr

pub const fn adrdy(&self) -> bool

ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it

pub fn set_adrdy(&mut self, val: bool)

ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it

pub const fn eosmp(&self) -> bool

End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase

pub fn set_eosmp(&mut self, val: bool)

End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase

pub const fn eoc(&self) -> bool

End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register

pub fn set_eoc(&mut self, val: bool)

End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register

pub const fn eos(&self) -> bool

End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it

pub fn set_eos(&mut self, val: bool)

End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it

pub const fn ovr(&self) -> bool

overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it

pub fn set_ovr(&mut self, val: bool)

overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it

pub const fn jeoc(&self) -> bool

Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register

pub fn set_jeoc(&mut self, val: bool)

Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register

pub const fn jeos(&self) -> bool

Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it

pub fn set_jeos(&mut self, val: bool)

Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it

pub const fn awd(&self, n: usize) -> bool

Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software.

pub fn set_awd(&mut self, n: usize, val: bool)

Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software.

pub const fn jqovf(&self) -> bool

Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information

pub fn set_jqovf(&mut self, val: bool)

Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information

Trait Implementations

impl Clone for Isr

fn clone(&self) -> Isr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Isr

fn default() -> Isr

Returns the “default value” for a type.

impl PartialEq for Isr

fn eq(&self, other: &Isr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Isr

impl Eq for Isr

impl StructuralPartialEq for Isr