Struct stm32_metapac::fmc::regs::Sdcr

#[repr(transparent)]
pub struct Sdcr(pub u32);

Expand description

SDRAM control registers 1.

Tuple Fields§

§0: u32

Implementations§

§

impl Sdcr

pub const fn nc(&self) -> Nc

Number of column address bits These bits define the number of bits of a column address.

pub fn set_nc(&mut self, val: Nc)

Number of column address bits These bits define the number of bits of a column address.

pub const fn nr(&self) -> Nr

Number of row address bits These bits define the number of bits of a row address.

pub fn set_nr(&mut self, val: Nr)

Number of row address bits These bits define the number of bits of a row address.

pub const fn mwid(&self) -> Mwid

Memory data bus width. These bits define the memory device width.

pub fn set_mwid(&mut self, val: Mwid)

Memory data bus width. These bits define the memory device width.

pub const fn nb(&self) -> Nb

Number of internal banks This bit sets the number of internal banks.

pub fn set_nb(&mut self, val: Nb)

Number of internal banks This bit sets the number of internal banks.

pub const fn cas(&self) -> Cas

CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles.

pub fn set_cas(&mut self, val: Cas)

CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles.

pub const fn wp(&self) -> bool

Write protection This bit enables write mode access to the SDRAM bank.

pub fn set_wp(&mut self, val: bool)

Write protection This bit enables write mode access to the SDRAM bank.

pub const fn sdclk(&self) -> Sdclk

SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care.

pub fn set_sdclk(&mut self, val: Sdclk)

SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register are don’t care.

pub const fn rburst(&self) -> bool

Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care.

pub fn set_rburst(&mut self, val: bool)

Burst read This bit enables Burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is don’t care.

pub const fn rpipe(&self) -> Rpipe

Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.

pub fn set_rpipe(&mut self, val: Rpipe)

Read pipe These bits define the delay, in clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only.