Struct stm32_metapac::fmc::regs::Sdtr

#[repr(transparent)]
pub struct Sdtr(pub u32);

SDRAM timing registers 1.

Tuple Fields

0: u32

Implementations

impl Sdtr

pub const fn tmrd(&self) -> u8

Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ….

pub fn set_tmrd(&mut self, val: u8)

Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ….

pub const fn txsr(&self) -> u8

Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. …. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.

pub fn set_txsr(&mut self, val: u8)

Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. …. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.

pub const fn tras(&self) -> u8

Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ….

pub fn set_tras(&mut self, val: u8)

Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ….

pub const fn trc(&self) -> u8

Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. …. Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.

pub fn set_trc(&mut self, val: u8)

Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. …. Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.

pub const fn twr(&self) -> u8

Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. …. Note: TWR must be programmed to match the write recovery time (t_WR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank.

pub fn set_twr(&mut self, val: u8)

Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. …. Note: TWR must be programmed to match the write recovery time (t_WR) defined in the SDRAM datasheet, and to guarantee that: Note: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank.

pub const fn trp(&self) -> u8

Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. …. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.

pub fn set_trp(&mut self, val: u8)

Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. …. Note: The corresponding bits in the FMC_SDTR2 register are don’t care.

pub const fn trcd(&self) -> u8

Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ….

pub fn set_trcd(&mut self, val: u8)

Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ….

Trait Implementations

impl Clone for Sdtr

fn clone(&self) -> Sdtr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Sdtr

fn default() -> Sdtr

Returns the “default value” for a type.

impl PartialEq for Sdtr

fn eq(&self, other: &Sdtr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Sdtr

impl Eq for Sdtr

impl StructuralPartialEq for Sdtr