Struct stm32_metapac::fmc::regs::Bcr

#[repr(transparent)]
pub struct Bcr(pub u32);

Expand description

SRAM/NOR-Flash chip-select control register for bank 4.

Tuple Fields§

§0: u32

Implementations§

§

impl Bcr

pub const fn mbken(&self) -> bool

Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.

pub fn set_mbken(&mut self, val: bool)

Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.

pub const fn muxen(&self) -> bool

Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

pub fn set_muxen(&mut self, val: bool)

Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

pub const fn mtyp(&self) -> Mtyp

Memory type Defines the type of external memory attached to the corresponding memory bank.

pub fn set_mtyp(&mut self, val: Mtyp)

Memory type Defines the type of external memory attached to the corresponding memory bank.

pub const fn mwid(&self) -> Mwid

Memory data bus width Defines the external memory device width, valid for all type of memories.

pub fn set_mwid(&mut self, val: Mwid)

Memory data bus width Defines the external memory device width, valid for all type of memories.

pub const fn faccen(&self) -> bool

Flash access enable Enables NOR Flash memory access operations.

pub fn set_faccen(&mut self, val: bool)

Flash access enable Enables NOR Flash memory access operations.

pub const fn bursten(&self) -> bool

Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.

pub fn set_bursten(&mut self, val: bool)

Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.

pub const fn waitpol(&self) -> Waitpol

Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.

pub fn set_waitpol(&mut self, val: Waitpol)

Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.

pub const fn waitcfg(&self) -> Waitcfg

Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

pub fn set_waitcfg(&mut self, val: Waitcfg)

Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

pub const fn wren(&self) -> bool

Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC.

pub fn set_wren(&mut self, val: bool)

Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC.

pub const fn waiten(&self) -> bool

Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.

pub fn set_waiten(&mut self, val: bool)

Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.

pub const fn extmod(&self) -> bool

Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

pub fn set_extmod(&mut self, val: bool)

Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

pub const fn asyncwait(&self) -> bool

Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.

pub fn set_asyncwait(&mut self, val: bool)

Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.

pub const fn cpsize(&self) -> Cpsize

CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.

pub fn set_cpsize(&mut self, val: Cpsize)

CRAM page size These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved.

pub const fn cburstrw(&self) -> Cburstrw

Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.

pub fn set_cburstrw(&mut self, val: Cburstrw)

Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.

pub const fn cclken(&self) -> bool

Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

pub fn set_cclken(&mut self, val: bool)

Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

pub const fn wfdis(&self) -> bool

Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.

pub fn set_wfdis(&mut self, val: bool)

Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.

pub const fn nblset(&self) -> u8

Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low.

pub fn set_nblset(&mut self, val: u8)

Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low.

pub const fn fmcen(&self) -> bool

FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.

pub fn set_fmcen(&mut self, val: bool)

FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the FMC_BCR1 register.