Struct stm32_metapac::pwr::regs::Csr1

#[repr(transparent)]
pub struct Csr1(pub u32);

PWR control status register 1

Tuple Fields

0: u32

Implementations

impl Csr1

pub const fn pvdo(&self) -> bool

Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

pub fn set_pvdo(&mut self, val: bool)

Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

pub const fn actvosrdy(&self) -> bool

Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3).

pub fn set_actvosrdy(&mut self, val: bool)

Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3).

pub const fn actvos(&self) -> u8

VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU.

pub fn set_actvos(&mut self, val: u8)

VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU.

pub const fn avdo(&self) -> bool

Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.

pub fn set_avdo(&mut self, val: bool)

Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.

Trait Implementations

impl Clone for Csr1

fn clone(&self) -> Csr1

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Csr1

fn default() -> Csr1

Returns the “default value” for a type.

impl PartialEq for Csr1

fn eq(&self, other: &Csr1) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Csr1

impl Eq for Csr1

impl StructuralPartialEq for Csr1