Struct stm32_metapac::pwr::regs::Cpucr

#[repr(transparent)]
pub struct Cpucr(pub u32);

This register allows controlling CPU1 power.

Tuple Fields

0: u32

Implementations

impl Cpucr

pub const fn pdds_d1(&self) -> bool

D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain.

pub fn set_pdds_d1(&mut self, val: bool)

D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain.

pub const fn pdds_d2(&self) -> bool

D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain.

pub fn set_pdds_d2(&mut self, val: bool)

D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain.

pub const fn pdds_d3(&self) -> bool

System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain.

pub fn set_pdds_d3(&mut self, val: bool)

System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain.

pub const fn stopf(&self) -> bool

STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit.

pub fn set_stopf(&mut self, val: bool)

STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit.

pub const fn sbf(&self) -> bool

System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit

pub fn set_sbf(&mut self, val: bool)

System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit

pub const fn sbf_d1(&self) -> bool

D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode.

pub fn set_sbf_d1(&mut self, val: bool)

D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode.

pub const fn sbf_d2(&self) -> bool

D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode.

pub fn set_sbf_d2(&mut self, val: bool)

D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode.

pub const fn cssf(&self) -> bool

Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware.

pub fn set_cssf(&mut self, val: bool)

Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware.

pub const fn run_d3(&self) -> bool

Keep system D3 domain in Run mode regardless of the CPU sub-systems modes

pub fn set_run_d3(&mut self, val: bool)

Keep system D3 domain in Run mode regardless of the CPU sub-systems modes

Trait Implementations

impl Clone for Cpucr

fn clone(&self) -> Cpucr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cpucr

fn default() -> Cpucr

Returns the “default value” for a type.

impl PartialEq for Cpucr

fn eq(&self, other: &Cpucr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cpucr

impl Eq for Cpucr

impl StructuralPartialEq for Cpucr