Struct stm32_metapac::dts::regs::Cfgr1

#[repr(transparent)]
pub struct Cfgr1(pub u32);

Expand description

Temperature sensor configuration register 1.

Tuple Fields§

§0: u32

Implementations§

§

impl Cfgr1

pub const fn en(&self) -> bool

Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready.

pub fn set_en(&mut self, val: bool)

Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready.

pub const fn start(&self) -> bool

Start frequency measurement on temperature sensor 1 This bit is set and cleared by software.

pub fn set_start(&mut self, val: bool)

Start frequency measurement on temperature sensor 1 This bit is set and cleared by software.

pub const fn intrig_sel(&self) -> u8

Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 19.3.10: Trigger input.

pub fn set_intrig_sel(&mut self, val: u8)

Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 19.3.10: Trigger input.

pub const fn smp_time(&self) -> u8

Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE.

pub fn set_smp_time(&mut self, val: u8)

Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE.

pub const fn refclk_sel(&self) -> bool

Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE).

pub fn set_refclk_sel(&mut self, val: bool)

Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE).

pub const fn q_meas_opt(&self) -> bool

Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1).

pub fn set_q_meas_opt(&mut self, val: bool)

Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1).

pub const fn hsref_clk_div(&self) -> u8

High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). …

pub fn set_hsref_clk_div(&mut self, val: u8)

High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). …