Struct stm32_metapac::pssi::regs::Cr

#[repr(transparent)]
pub struct Cr(pub u32);

PSSI control register.

Tuple Fields

0: u32

Implementations

impl Cr

pub const fn ckpol(&self) -> Ckpol

Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN.

pub fn set_ckpol(&mut self, val: Ckpol)

Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN.

pub const fn depol(&self) -> Depol

Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface.

pub fn set_depol(&mut self, val: Depol)

Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface.

pub const fn rdypol(&self) -> Rdypol

Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface.

pub fn set_rdypol(&mut self, val: Rdypol)

Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface.

pub const fn edm(&self) -> Edm

Extended data mode.

pub fn set_edm(&mut self, val: Edm)

Extended data mode.

pub const fn enable(&self) -> bool

PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time.

pub fn set_enable(&mut self, val: bool)

PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time.

pub const fn derdycfg(&self) -> Derdycfg

Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity.

pub fn set_derdycfg(&mut self, val: Derdycfg)

Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity.

pub const fn dmaen(&self) -> bool

DMA enable bit.

pub fn set_dmaen(&mut self, val: bool)

DMA enable bit.

pub const fn outen(&self) -> Outen

Data direction selection bit.

pub fn set_outen(&mut self, val: Outen)

Data direction selection bit.

Trait Implementations

impl Clone for Cr

fn clone(&self) -> Cr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cr

fn default() -> Cr

Returns the “default value” for a type.

impl PartialEq for Cr

fn eq(&self, other: &Cr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cr

impl Eq for Cr

impl StructuralPartialEq for Cr