Struct Rcc 

pub struct Rcc { /* private fields */ }

RCC register block.

Implementations

impl Rcc

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn cr(self) -> Reg<Cr, RW>

RCC source control register.

pub const fn hsicfgr(self) -> Reg<Hsicfgr, RW>

RCC HSI calibration register.

pub const fn crrcr(self) -> Reg<Crrcr, R>

RCC clock recovery RC register.

pub const fn csicfgr(self) -> Reg<Csicfgr, RW>

RCC CSI calibration register.

pub const fn cfgr(self) -> Reg<Cfgr, RW>

RCC clock configuration register.

pub const fn cdcfgr(self) -> Reg<Cdcfgr, RW>

RCC CPU domain clock configuration register.

pub const fn bmcfgr(self) -> Reg<Bmcfgr, RW>

RCC AHB clock configuration register.

pub const fn apbcfgr(self) -> Reg<Apbcfgr, RW>

RCC APB clocks configuration register.

pub const fn pllckselr(self) -> Reg<Pllckselr, RW>

RCC PLLs clock source selection register.

pub const fn pllcfgr(self) -> Reg<Pllcfgr, RW>

RCC PLLs configuration register.

pub const fn pll1divr1(self) -> Reg<Pll1divr1, RW>

RCC PLL1 dividers configuration register 1.

pub const fn pll1fracr(self) -> Reg<Pll1fracr, RW>

RCC PLL1 fractional divider register.

pub const fn pll2divr1(self) -> Reg<Pll2divr1, RW>

RCC PLL2 dividers configuration register 1.

pub const fn pll2fracr(self) -> Reg<Pll2fracr, RW>

RCC PLL2 fractional divider register.

pub const fn pll3divr1(self) -> Reg<Pll3divr1, RW>

RCC PLL3 dividers configuration register 1.

pub const fn pll3fracr(self) -> Reg<Pll3fracr, RW>

RCC PLL3 fractional divider register.

pub const fn ccipr1(self) -> Reg<Ccipr1, RW>

RCC peripheral kernel clock selection register 1.

pub const fn ccipr2(self) -> Reg<Ccipr2, RW>

RCC peripheral kernel clock selection register 2.

pub const fn ccipr3(self) -> Reg<Ccipr3, RW>

RCC peripheral kernel clock selection register 3.

pub const fn ccipr4(self) -> Reg<Ccipr4, RW>

RCC peripheral kernel clock selection register 4.

pub const fn cier(self) -> Reg<Cier, RW>

RCC clock source interrupt enable register.

pub const fn cifr(self) -> Reg<Cifr, R>

RCC clock source interrupt flag register.

pub const fn cicr(self) -> Reg<Cicr, W>

RCC clock source interrupt clear register.

pub const fn bdcr(self) -> Reg<Bdcr, RW>

RCC Backup domain control register.

pub const fn csr(self) -> Reg<Csr, RW>

RCC clock control and status register.

pub const fn ahb5rstr(self) -> Reg<Ahb5rstr, RW>

RCC AHB5 peripheral reset register.

pub const fn ahb1rstr(self) -> Reg<Ahb1rstr, RW>

RCC AHB1 peripheral reset register.

pub const fn ahb2rstr(self) -> Reg<Ahb2rstr, RW>

RCC AHB2 peripheral reset register.

pub const fn ahb4rstr(self) -> Reg<Ahb4rstr, RW>

RCC AHB4 peripheral reset register.

pub const fn apb1rstr1(self) -> Reg<Apb1rstr1, RW>

RCC APB1 peripheral reset register 1.

pub const fn apb1rstr2(self) -> Reg<Apb1rstr2, RW>

RCC APB1 peripheral reset register 2.

pub const fn apb2rstr(self) -> Reg<Apb2rstr, RW>

RCC APB2 peripheral reset register.

pub const fn apb4rstr(self) -> Reg<Apb4rstr, RW>

RCC APB4 peripheral reset register.

pub const fn ahb3rstr(self) -> Reg<Ahb3rstr, RW>

RCC AHB3 peripheral reset register.

pub const fn ckgdisr(self) -> Reg<Ckgdisr, RW>

RCC AXI clocks gating disable register.

pub const fn pll1divr2(self) -> Reg<Pll1divr2, RW>

RCC PLL1 dividers configuration register 2.

pub const fn pll2divr2(self) -> Reg<Pll2divr2, RW>

RCC PLL2 dividers configuration register 2.

pub const fn pll3divr2(self) -> Reg<Pll3divr2, RW>

RCC PLL3 dividers configuration register 2.

pub const fn pll1sscgr(self) -> Reg<Pll1sscgr, RW>

RCC PLL1 Spread Spectrum Clock Generator register.

pub const fn pll2sscgr(self) -> Reg<Pll2sscgr, RW>

RCC PLL2 Spread Spectrum Clock Generator register.

pub const fn pll3sscgr(self) -> Reg<Pll3sscgr, RW>

RCC PLL3 Spread Spectrum Clock Generator register.

pub const fn ckprotr(self) -> Reg<Ckprotr, RW>

RCC clock protection register.

pub const fn rsr(self) -> Reg<Rsr, RW>

RCC Reset status register.

pub const fn ahb5enr(self) -> Reg<Ahb5enr, RW>

RCC AHB5 clock enable register.

pub const fn ahb1enr(self) -> Reg<Ahb1enr, RW>

RCC AHB1 clock enable register.

pub const fn ahb2enr(self) -> Reg<Ahb2enr, RW>

RCC AHB2 clock enable register.

pub const fn ahb4enr(self) -> Reg<Ahb4enr, RW>

RCC AHB4 clock enable register.

pub const fn apb1enr1(self) -> Reg<Apb1enr1, RW>

RCC APB1 clock enable register 1.

pub const fn apb1enr2(self) -> Reg<Apb1enr2, RW>

RCC APB1 clock enable register 2.

pub const fn apb2enr(self) -> Reg<Apb2enr, RW>

RCC APB2 clock enable register.

pub const fn apb4enr(self) -> Reg<Apb4enr, RW>

RCC APB4 clock enable register.

pub const fn ahb3enr(self) -> Reg<Ahb3enr, RW>

RCC AHB3 clock enable register.

pub const fn ahb5lpenr(self) -> Reg<Ahb5lpenr, RW>

RCC AHB5 low-power clock enable register.

pub const fn ahb1lpenr(self) -> Reg<Ahb1lpenr, RW>

RCC AHB1 low-power clock enable register.

pub const fn ahb2lpenr(self) -> Reg<Ahb2lpenr, RW>

RCC AHB2 low-power clock enable register.

pub const fn ahb4lpenr(self) -> Reg<Ahb4lpenr, RW>

RCC AHB4 low-power clock enable register.

pub const fn ahb3lpenr(self) -> Reg<Ahb3lpenr, RW>

RCC AHB3 low-power clock enable register.

pub const fn apb1lpenr1(self) -> Reg<Apb1lpenr1, RW>

RCC APB1 low-power clock enable register 1.

pub const fn apb1lpenr2(self) -> Reg<Apb1lpenr2, RW>

RCC APB1 low-power clock enable register 2.

pub const fn apb2lpenr(self) -> Reg<Apb2lpenr, RW>

RCC APB2 low-power clock enable register.

pub const fn apb4lpenr(self) -> Reg<Apb4lpenr, RW>

RCC APB4 low-power clock enable register.

Trait Implementations

impl Clone for Rcc

fn clone(&self) -> Rcc

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Rcc

impl Eq for Rcc

impl PartialEq for Rcc

fn eq(&self, other: &Rcc) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl Send for Rcc

impl StructuralPartialEq for Rcc

impl Sync for Rcc