Struct Pllcfgr
#[repr(transparent)]pub struct Pllcfgr(pub u32);Expand description
RCC PLLs configuration register.
Tuple Fields§
§0: u32Implementations§
§impl Pllcfgr
impl Pllcfgr
pub const fn pll1fracen(&self) -> bool
pub const fn pll1fracen(&self) -> bool
PLL1 fractional latch enable.
pub const fn set_pll1fracen(&mut self, val: bool)
pub const fn set_pll1fracen(&mut self, val: bool)
PLL1 fractional latch enable.
pub const fn pll1vcosel(&self) -> Pll1vcosel
pub const fn pll1vcosel(&self) -> Pll1vcosel
PLL1 VCO selection.
pub const fn set_pll1vcosel(&mut self, val: Pll1vcosel)
pub const fn set_pll1vcosel(&mut self, val: Pll1vcosel)
PLL1 VCO selection.
pub const fn pll1sscgen(&self) -> bool
pub const fn pll1sscgen(&self) -> bool
PLL1 SSCG enable.
pub const fn set_pll1sscgen(&mut self, val: bool)
pub const fn set_pll1sscgen(&mut self, val: bool)
PLL1 SSCG enable.
pub const fn set_pll1rge(&mut self, val: Pll1rge)
pub const fn set_pll1rge(&mut self, val: Pll1rge)
PLL1 input frequency range.
pub const fn set_pll1pen(&mut self, val: bool)
pub const fn set_pll1pen(&mut self, val: bool)
PLL1 DIVP divider output enable.
pub const fn set_pll1qen(&mut self, val: bool)
pub const fn set_pll1qen(&mut self, val: bool)
PLL1 DIVQ divider output enable.
pub const fn set_pll1sen(&mut self, val: bool)
pub const fn set_pll1sen(&mut self, val: bool)
PLL1 DIVS divider output enable.
pub const fn pll2fraclen(&self) -> bool
pub const fn pll2fraclen(&self) -> bool
PLL2 fractional latch enable.
pub const fn set_pll2fraclen(&mut self, val: bool)
pub const fn set_pll2fraclen(&mut self, val: bool)
PLL2 fractional latch enable.
pub const fn pll2vcosel(&self) -> Pll2vcosel
pub const fn pll2vcosel(&self) -> Pll2vcosel
PLL2 VCO selection.
pub const fn set_pll2vcosel(&mut self, val: Pll2vcosel)
pub const fn set_pll2vcosel(&mut self, val: Pll2vcosel)
PLL2 VCO selection.
pub const fn pll2sscgen(&self) -> bool
pub const fn pll2sscgen(&self) -> bool
PLL2 SSCG enable.
pub const fn set_pll2sscgen(&mut self, val: bool)
pub const fn set_pll2sscgen(&mut self, val: bool)
PLL2 SSCG enable.
pub const fn set_pll2rge(&mut self, val: Pll2rge)
pub const fn set_pll2rge(&mut self, val: Pll2rge)
PLL2 input frequency range.
pub const fn set_pll2pen(&mut self, val: bool)
pub const fn set_pll2pen(&mut self, val: bool)
PLL2 DIVP divider output enable.
pub const fn set_pll2qen(&mut self, val: bool)
pub const fn set_pll2qen(&mut self, val: bool)
PLL2 DIVQ divider output enable.
pub const fn set_pll2ren(&mut self, val: bool)
pub const fn set_pll2ren(&mut self, val: bool)
PLL2 DIVR divider output enable.
pub const fn set_pll2sen(&mut self, val: bool)
pub const fn set_pll2sen(&mut self, val: bool)
PLL2 DIVS divider output enable.
pub const fn set_pll2ten(&mut self, val: bool)
pub const fn set_pll2ten(&mut self, val: bool)
PLL2 DIVT divider output enable.
pub const fn pll3fracen(&self) -> bool
pub const fn pll3fracen(&self) -> bool
PLL3 fractional latch enable.
pub const fn set_pll3fracen(&mut self, val: bool)
pub const fn set_pll3fracen(&mut self, val: bool)
PLL3 fractional latch enable.
pub const fn pll3vcosel(&self) -> Pll3vcosel
pub const fn pll3vcosel(&self) -> Pll3vcosel
PLL3 VCO selection.
pub const fn set_pll3vcosel(&mut self, val: Pll3vcosel)
pub const fn set_pll3vcosel(&mut self, val: Pll3vcosel)
PLL3 VCO selection.
pub const fn pll3sscgen(&self) -> bool
pub const fn pll3sscgen(&self) -> bool
PLL3 SSCG enable.
pub const fn set_pll3sscgen(&mut self, val: bool)
pub const fn set_pll3sscgen(&mut self, val: bool)
PLL3 SSCG enable.
pub const fn set_pll3rge(&mut self, val: Pll3rge)
pub const fn set_pll3rge(&mut self, val: Pll3rge)
PLL3 input frequency range.
pub const fn set_pll3pen(&mut self, val: bool)
pub const fn set_pll3pen(&mut self, val: bool)
PLL3 DIVP divider output enable.
pub const fn set_pll3qen(&mut self, val: bool)
pub const fn set_pll3qen(&mut self, val: bool)
PLL3 DIVQ divider output enable.
pub const fn set_pll3ren(&mut self, val: bool)
pub const fn set_pll3ren(&mut self, val: bool)
PLL3 DIVR divider output enable.
pub const fn set_pll3sen(&mut self, val: bool)
pub const fn set_pll3sen(&mut self, val: bool)
PLL3 DIVS divider output enable.