Struct Ckgdisr 

#[repr(transparent)]
pub struct Ckgdisr(pub u32);

RCC AXI clocks gating disable register.

Tuple Fields

0: u32

Implementations

impl Ckgdisr

pub const fn axickg(&self) -> bool

AXI interconnect matrix clock gating disable.

pub const fn set_axickg(&mut self, val: bool)

AXI interconnect matrix clock gating disable.

pub const fn ahbmckg(&self) -> bool

AXI AHB matrix port clock gating disable.

pub const fn set_ahbmckg(&mut self, val: bool)

AXI AHB matrix port clock gating disable.

pub const fn sdmmc1ckg(&self) -> bool

AXI SDMMC1 port clock gating disable.

pub const fn set_sdmmc1ckg(&mut self, val: bool)

AXI SDMMC1 port clock gating disable.

pub const fn hpdma1ckg(&self) -> bool

AXI HPDMA1 port clock gating disable.

pub const fn set_hpdma1ckg(&mut self, val: bool)

AXI HPDMA1 port clock gating disable.

pub const fn cpuckg(&self) -> bool

AXI CPU port clock gating disable.

pub const fn set_cpuckg(&mut self, val: bool)

AXI CPU port clock gating disable.

pub const fn npu0ckg(&self) -> bool

AXI NPU port 0 clock gating disable.

pub const fn set_npu0ckg(&mut self, val: bool)

AXI NPU port 0 clock gating disable.

pub const fn npu1ckg(&self) -> bool

AXI NPU port 1 clock gating disable.

pub const fn set_npu1ckg(&mut self, val: bool)

AXI NPU port 1 clock gating disable.

pub const fn ahbsckg(&self) -> bool

AHBS AXI manager port clock gating disable.

pub const fn set_ahbsckg(&mut self, val: bool)

AHBS AXI manager port clock gating disable.

pub const fn ahbicckg(&self) -> bool

AHB interconnect AXI manager port clock gating disable.

pub const fn set_ahbicckg(&mut self, val: bool)

AHB interconnect AXI manager port clock gating disable.

pub const fn fmcckg(&self) -> bool

FMC AXI manager port clock gating disable.

pub const fn set_fmcckg(&mut self, val: bool)

FMC AXI manager port clock gating disable.

pub const fn xspi1ckg(&self) -> bool

XSPI1 AXI manager port clock gating disable.

pub const fn set_xspi1ckg(&mut self, val: bool)

XSPI1 AXI manager port clock gating disable.

pub const fn axisram4ckg(&self) -> bool

AXISRAM4 AXI manager port clock gating disable.

pub const fn set_axisram4ckg(&mut self, val: bool)

AXISRAM4 AXI manager port clock gating disable.

pub const fn axisram3ckg(&self) -> bool

AXISRAM3 AXI manager port clock gating disable.

pub const fn set_axisram3ckg(&mut self, val: bool)

AXISRAM3 AXI manager port clock gating disable.

pub const fn axisram2ckg(&self) -> bool

AXISRAM2 AXI manager port clock gating disable.

pub const fn set_axisram2ckg(&mut self, val: bool)

AXISRAM2 AXI manager port clock gating disable.

pub const fn axisram1ckg(&self) -> bool

AXISRAM1 AXI manager port clock gating disable.

pub const fn set_axisram1ckg(&mut self, val: bool)

AXISRAM1 AXI manager port clock gating disable.

pub const fn flashckg(&self) -> bool

Flash interface (FLIFT) AXI manager port clock gating disable.

pub const fn set_flashckg(&mut self, val: bool)

Flash interface (FLIFT) AXI manager port clock gating disable.

pub const fn extickg(&self) -> bool

EXTI clock gating disable.

pub const fn set_extickg(&mut self, val: bool)

EXTI clock gating disable.

pub const fn jtagckg(&self) -> bool

JTAG automatic clock gating disabling.

pub const fn set_jtagckg(&mut self, val: bool)

JTAG automatic clock gating disabling.

Trait Implementations

impl Clone for Ckgdisr

fn clone(&self) -> Ckgdisr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Ckgdisr

impl Debug for Ckgdisr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Ckgdisr

fn default() -> Ckgdisr

Returns the “default value” for a type.

impl Eq for Ckgdisr

impl PartialEq for Ckgdisr

fn eq(&self, other: &Ckgdisr) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for Ckgdisr