Struct stm32_metapac::rcc::regs::Apb1enr1

#[repr(transparent)]
pub struct Apb1enr1(pub u32);

Expand description

RCC APB1 clock enable register 1.

Tuple Fields§

§0: u32

Implementations§

§

impl Apb1enr1

pub const fn tim2en(&self) -> bool

TIM2 peripheral clock enable Set and reset by software.

pub fn set_tim2en(&mut self, val: bool)

TIM2 peripheral clock enable Set and reset by software.

pub const fn tim3en(&self) -> bool

TIM3 peripheral clock enable Set and reset by software.

pub fn set_tim3en(&mut self, val: bool)

TIM3 peripheral clock enable Set and reset by software.

pub const fn tim4en(&self) -> bool

TIM4 peripheral clock enable Set and reset by software.

pub fn set_tim4en(&mut self, val: bool)

TIM4 peripheral clock enable Set and reset by software.

pub const fn tim5en(&self) -> bool

TIM5 peripheral clock enable Set and reset by software.

pub fn set_tim5en(&mut self, val: bool)

TIM5 peripheral clock enable Set and reset by software.

pub const fn tim6en(&self) -> bool

TIM6 peripheral clock enable Set and reset by software.

pub fn set_tim6en(&mut self, val: bool)

TIM6 peripheral clock enable Set and reset by software.

pub const fn tim7en(&self) -> bool

TIM7 peripheral clock enable Set and reset by software.

pub fn set_tim7en(&mut self, val: bool)

TIM7 peripheral clock enable Set and reset by software.

pub const fn tim12en(&self) -> bool

TIM12 peripheral clock enable Set and reset by software.

pub fn set_tim12en(&mut self, val: bool)

TIM12 peripheral clock enable Set and reset by software.

pub const fn tim13en(&self) -> bool

TIM13 peripheral clock enable Set and reset by software.

pub fn set_tim13en(&mut self, val: bool)

TIM13 peripheral clock enable Set and reset by software.

pub const fn tim14en(&self) -> bool

TIM14 peripheral clock enable Set and reset by software.

pub fn set_tim14en(&mut self, val: bool)

TIM14 peripheral clock enable Set and reset by software.

pub const fn lptim1en(&self) -> bool

LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock.

pub fn set_lptim1en(&mut self, val: bool)

LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock.

pub const fn wwdgen(&self) -> bool

WWDG clock enable Set by software, and reset by hardware when a system reset occurs.

pub fn set_wwdgen(&mut self, val: bool)

WWDG clock enable Set by software, and reset by hardware when a system reset occurs.

pub const fn spi2en(&self) -> bool

SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.

pub fn set_spi2en(&mut self, val: bool)

SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.

pub const fn spi3en(&self) -> bool

SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.

pub fn set_spi3en(&mut self, val: bool)

SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock.

pub const fn spdifrxen(&self) -> bool

SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock.

pub fn set_spdifrxen(&mut self, val: bool)

SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock.

pub const fn usart2en(&self) -> bool

USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.

pub fn set_usart2en(&mut self, val: bool)

USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.

pub const fn usart3en(&self) -> bool

USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.

pub fn set_usart3en(&mut self, val: bool)

USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.

pub const fn uart4en(&self) -> bool

UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.

pub fn set_uart4en(&mut self, val: bool)

UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock.