Struct stm32_metapac::rcc::regs::Pllcfgr

#[repr(transparent)]
pub struct Pllcfgr(pub u32);

Expand description

RCC PLLs configuration register.

Tuple Fields§

§0: u32

Implementations§

§

impl Pllcfgr

pub const fn pllfracen(&self, n: usize) -> bool

PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information.

pub fn set_pllfracen(&mut self, n: usize, val: bool)

PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information.

pub const fn pllvcosel(&self, n: usize) -> Pllvcosel

PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (F_{ref1_ck} must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (F_{ref1_ck} must be between 1 and 2 MHz).

pub fn set_pllvcosel(&mut self, n: usize, val: Pllvcosel)

PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (F_{ref1_ck} must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (F_{ref1_ck} must be between 1 and 2 MHz).

pub const fn pllsscgen(&self, n: usize) -> bool

PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks.

pub fn set_pllsscgen(&mut self, n: usize, val: bool)

PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks.

pub const fn pllrge(&self, n: usize) -> Pllrge

PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1.

pub fn set_pllrge(&mut self, n: usize, val: Pllrge)

PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1.

pub const fn divpen(&self, n: usize) -> bool

PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.

pub fn set_divpen(&mut self, n: usize, val: bool)

PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.

pub const fn divqen(&self, n: usize) -> bool

PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.

pub fn set_divqen(&mut self, n: usize, val: bool)

PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.

pub const fn divren(&self, n: usize) -> bool

PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used.

pub fn set_divren(&mut self, n: usize, val: bool)

PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used.

pub const fn divsen(&self, n: usize) -> bool

PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used.

pub fn set_divsen(&mut self, n: usize, val: bool)

PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used.

pub const fn divten(&self, n: usize) -> bool

PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used.

pub fn set_divten(&mut self, n: usize, val: bool)

PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used.