Struct stm32_metapac::rcc::regs::Plldivr

#[repr(transparent)]
pub struct Plldivr(pub u32);

RCC PLL1 dividers configuration register 1.

Tuple Fields

0: u32

Implementations

impl Plldivr

pub const fn plln(&self) -> Plln

multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ……….: not used … … Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = F_{ref1_ck} x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency F_{ref1_ck} must be between 1 and 16 MHz.

pub fn set_plln(&mut self, val: Plln)

multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ……….: not used … … Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = F_{ref1_ck} x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency F_{ref1_ck} must be between 1 and 16 MHz.

pub const fn pllp(&self) -> Plldiv

PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. …

pub fn set_pllp(&mut self, val: Plldiv)

PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. …

pub const fn pllq(&self) -> Plldiv

PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. …

pub fn set_pllq(&mut self, val: Plldiv)

PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. …

pub const fn pllr(&self) -> Plldiv

PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. …

pub fn set_pllr(&mut self, val: Plldiv)

PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. …

Trait Implementations

impl Clone for Plldivr

fn clone(&self) -> Plldivr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Plldivr

fn default() -> Plldivr

Returns the “default value” for a type.

impl PartialEq for Plldivr

fn eq(&self, other: &Plldivr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Plldivr

impl Eq for Plldivr

impl StructuralPartialEq for Plldivr