Struct stm32_metapac::rcc::regs::Rsr

#[repr(transparent)]
pub struct Rsr(pub u32);

RCC Reset status register.

Tuple Fields

0: u32

Implementations

impl Rsr

pub const fn rmvf(&self) -> bool

remove reset flag Set and reset by software to reset the value of the reset flags.

pub fn set_rmvf(&mut self, val: bool)

remove reset flag Set and reset by software to reset the value of the reset flags.

pub const fn oblrstf(&self) -> bool

Option byte loading reset flag ⁽¹⁾ Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs.

pub fn set_oblrstf(&mut self, val: bool)

Option byte loading reset flag ⁽¹⁾ Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs.

pub const fn borrstf(&self) -> bool

BOR reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst).

pub fn set_borrstf(&mut self, val: bool)

BOR reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst).

pub const fn pinrstf(&self) -> bool

pin reset flag (NRST) ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs.

pub fn set_pinrstf(&mut self, val: bool)

pin reset flag (NRST) ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs.

pub const fn porrstf(&self) -> bool

POR/PDR reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs.

pub fn set_porrstf(&mut self, val: bool)

POR/PDR reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs.

pub const fn sftrstf(&self) -> bool

system reset from CPU reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7.

pub fn set_sftrstf(&mut self, val: bool)

system reset from CPU reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7.

pub const fn iwdgrstf(&self) -> bool

independent watchdog reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs.

pub fn set_iwdgrstf(&mut self, val: bool)

independent watchdog reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs.

pub const fn wwdgrstf(&self) -> bool

window watchdog reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs.

pub fn set_wwdgrstf(&mut self, val: bool)

window watchdog reset flag ⁽¹⁾ Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs.

pub const fn lpwrrstf(&self) -> bool

reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode,.

pub fn set_lpwrrstf(&mut self, val: bool)

reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode,.

Trait Implementations

impl Clone for Rsr

fn clone(&self) -> Rsr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Rsr

fn default() -> Rsr

Returns the “default value” for a type.

impl PartialEq for Rsr

fn eq(&self, other: &Rsr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Rsr

impl Eq for Rsr

impl StructuralPartialEq for Rsr