Struct stm32_metapac::iwdg::regs::Sr

#[repr(transparent)]
pub struct Sr(pub u32);

Expand description

Status register

Tuple Fields§

§0: u32

Implementations§

§

impl Sr

pub const fn pvu(&self) -> bool

Watchdog prescaler value update

pub fn set_pvu(&mut self, val: bool)

Watchdog prescaler value update

pub const fn rvu(&self) -> bool

Watchdog counter reload value update

pub fn set_rvu(&mut self, val: bool)

Watchdog counter reload value update

pub const fn wvu(&self) -> bool

Watchdog counter window value update

pub fn set_wvu(&mut self, val: bool)

Watchdog counter window value update

pub const fn ewu(&self) -> bool

Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset.

pub fn set_ewu(&mut self, val: bool)

Watchdog interrupt comparator value update This bit is set by hardware to indicate that an update of the interrupt comparator value (EWIT[11:0]) or an update of the EWIE is ongoing. It is reset by hardware when the update operation is completed in the VDD voltage domain (takes up to three periods of the IWDG kernel clock iwdg_ker_ck). The EWIT[11:0] and EWIE fields can be updated only when EWU bit is reset.

pub const fn ewif(&self) -> bool

Watchdog early interrupt flag This bit is set to ‘1’ by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to ‘1’.

pub fn set_ewif(&mut self, val: bool)

Watchdog early interrupt flag This bit is set to ‘1’ by hardware in order to indicate that an early interrupt is pending. This bit must be cleared by the software by writing the bit EWIC of IWDG_EWCR register to ‘1’.