Enum stm32_metapac::Interrupt

pub enum Interrupt {
    WWDG = 0,
    PVD_PVM = 1,
    TAMP_STAMP = 2,
    RTC_WKUP = 3,
    FLASH = 4,
    RCC = 5,
    EXTI0 = 6,
    EXTI1 = 7,
    EXTI2 = 8,
    EXTI3 = 9,
    EXTI4 = 10,
    DMA1_CHANNEL1 = 11,
    DMA1_CHANNEL2 = 12,
    DMA1_CHANNEL3 = 13,
    DMA1_CHANNEL4 = 14,
    DMA1_CHANNEL5 = 15,
    DMA1_CHANNEL6 = 16,
    DMA1_CHANNEL7 = 17,
    ADC1 = 18,
    CAN1_TX = 19,
    CAN1_RX0 = 20,
    CAN1_RX1 = 21,
    CAN1_SCE = 22,
    EXTI9_5 = 23,
    TIM1_BRK_TIM15 = 24,
    TIM1_UP_TIM16 = 25,
    TIM1_TRG_COM_TIM17 = 26,
    TIM1_CC = 27,
    TIM2 = 28,
    TIM3 = 29,
    TIM4 = 30,
    I2C1_EV = 31,
    I2C1_ER = 32,
    I2C2_EV = 33,
    I2C2_ER = 34,
    SPI1 = 35,
    SPI2 = 36,
    USART1 = 37,
    USART2 = 38,
    USART3 = 39,
    EXTI15_10 = 40,
    RTC_ALARM = 41,
    DFSDM1_FLT3 = 42,
    TIM8_BRK = 43,
    TIM8_UP = 44,
    TIM8_TRG_COM = 45,
    TIM8_CC = 46,
    FMC = 48,
    SDMMC1 = 49,
    TIM5 = 50,
    SPI3 = 51,
    UART4 = 52,
    UART5 = 53,
    TIM6_DAC = 54,
    TIM7 = 55,
    DMA2_CHANNEL1 = 56,
    DMA2_CHANNEL2 = 57,
    DMA2_CHANNEL3 = 58,
    DMA2_CHANNEL4 = 59,
    DMA2_CHANNEL5 = 60,
    DFSDM1_FLT0 = 61,
    DFSDM1_FLT1 = 62,
    DFSDM1_FLT2 = 63,
    COMP = 64,
    LPTIM1 = 65,
    LPTIM2 = 66,
    OTG_FS = 67,
    DMA2_CHANNEL6 = 68,
    DMA2_CHANNEL7 = 69,
    LPUART1 = 70,
    OCTOSPI1 = 71,
    I2C3_EV = 72,
    I2C3_ER = 73,
    SAI1 = 74,
    SAI2 = 75,
    OCTOSPI2 = 76,
    TSC = 77,
    RNG = 80,
    FPU = 81,
    CRS = 82,
    I2C4_ER = 83,
    I2C4_EV = 84,
    DCMI = 85,
    DMA2D = 90,
    DMAMUX1_OVR = 94,
}

Variants

WWDG = 0

0 - WWDG

PVD_PVM = 1

1 - PVD_PVM

TAMP_STAMP = 2

2 - TAMP_STAMP

RTC_WKUP = 3

3 - RTC_WKUP

FLASH = 4

4 - FLASH

RCC = 5

5 - RCC

EXTI0 = 6

6 - EXTI0

EXTI1 = 7

7 - EXTI1

EXTI2 = 8

8 - EXTI2

EXTI3 = 9

9 - EXTI3

EXTI4 = 10

10 - EXTI4

DMA1_CHANNEL1 = 11

11 - DMA1_CHANNEL1

DMA1_CHANNEL2 = 12

12 - DMA1_CHANNEL2

DMA1_CHANNEL3 = 13

13 - DMA1_CHANNEL3

DMA1_CHANNEL4 = 14

14 - DMA1_CHANNEL4

DMA1_CHANNEL5 = 15

15 - DMA1_CHANNEL5

DMA1_CHANNEL6 = 16

16 - DMA1_CHANNEL6

DMA1_CHANNEL7 = 17

17 - DMA1_CHANNEL7

ADC1 = 18

18 - ADC1

CAN1_TX = 19

19 - CAN1_TX

CAN1_RX0 = 20

20 - CAN1_RX0

CAN1_RX1 = 21

21 - CAN1_RX1

CAN1_SCE = 22

22 - CAN1_SCE

EXTI9_5 = 23

23 - EXTI9_5

TIM1_BRK_TIM15 = 24

24 - TIM1_BRK_TIM15

TIM1_UP_TIM16 = 25

25 - TIM1_UP_TIM16

TIM1_TRG_COM_TIM17 = 26

26 - TIM1_TRG_COM_TIM17

TIM1_CC = 27

27 - TIM1_CC

TIM2 = 28

28 - TIM2

TIM3 = 29

29 - TIM3

TIM4 = 30

30 - TIM4

I2C1_EV = 31

31 - I2C1_EV

I2C1_ER = 32

32 - I2C1_ER

I2C2_EV = 33

33 - I2C2_EV

I2C2_ER = 34

34 - I2C2_ER

SPI1 = 35

35 - SPI1

SPI2 = 36

36 - SPI2

USART1 = 37

37 - USART1

USART2 = 38

38 - USART2

USART3 = 39

39 - USART3

EXTI15_10 = 40

40 - EXTI15_10

RTC_ALARM = 41

41 - RTC_ALARM

DFSDM1_FLT3 = 42

42 - DFSDM1_FLT3

TIM8_BRK = 43

43 - TIM8_BRK

TIM8_UP = 44

44 - TIM8_UP

TIM8_TRG_COM = 45

45 - TIM8_TRG_COM

TIM8_CC = 46

46 - TIM8_CC

FMC = 48

48 - FMC

SDMMC1 = 49

49 - SDMMC1

TIM5 = 50

50 - TIM5

SPI3 = 51

51 - SPI3

UART4 = 52

52 - UART4

UART5 = 53

53 - UART5

TIM6_DAC = 54

54 - TIM6_DAC

TIM7 = 55

55 - TIM7

DMA2_CHANNEL1 = 56

56 - DMA2_CHANNEL1

DMA2_CHANNEL2 = 57

57 - DMA2_CHANNEL2

DMA2_CHANNEL3 = 58

58 - DMA2_CHANNEL3

DMA2_CHANNEL4 = 59

59 - DMA2_CHANNEL4

DMA2_CHANNEL5 = 60

60 - DMA2_CHANNEL5

DFSDM1_FLT0 = 61

61 - DFSDM1_FLT0

DFSDM1_FLT1 = 62

62 - DFSDM1_FLT1

DFSDM1_FLT2 = 63

63 - DFSDM1_FLT2

COMP = 64

64 - COMP

LPTIM1 = 65

65 - LPTIM1

LPTIM2 = 66

66 - LPTIM2

OTG_FS = 67

67 - OTG_FS

DMA2_CHANNEL6 = 68

68 - DMA2_CHANNEL6

DMA2_CHANNEL7 = 69

69 - DMA2_CHANNEL7

LPUART1 = 70

70 - LPUART1

OCTOSPI1 = 71

71 - OCTOSPI1

I2C3_EV = 72

72 - I2C3_EV

I2C3_ER = 73

73 - I2C3_ER

SAI1 = 74

74 - SAI1

SAI2 = 75

75 - SAI2

OCTOSPI2 = 76

76 - OCTOSPI2

TSC = 77

77 - TSC

RNG = 80

80 - RNG

FPU = 81

81 - FPU

CRS = 82

82 - CRS

I2C4_ER = 83

83 - I2C4_ER

I2C4_EV = 84

84 - I2C4_EV

DCMI = 85

85 - DCMI

DMA2D = 90

90 - DMA2D

DMAMUX1_OVR = 94

94 - DMAMUX1_OVR

Trait Implementations

impl Clone for Interrupt

fn clone(&self) -> Interrupt

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Interrupt

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl InterruptNumber for Interrupt

fn number(self) -> u16

Return the interrupt number associated with this variant.

impl PartialEq for Interrupt

fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Interrupt

impl Eq for Interrupt

impl StructuralPartialEq for Interrupt