Struct stm32_metapac::rcc::regs::Cfgr

#[repr(transparent)]
pub struct Cfgr(pub u32);

Expand description

Clock configuration register.

Tuple Fields§

§0: u32

Implementations§

§

impl Cfgr

pub const fn sw(&self) -> Sw

System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.

pub fn set_sw(&mut self, val: Sw)

System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.

pub const fn sws(&self) -> Sw

System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved.

pub fn set_sws(&mut self, val: Sw)

System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved.

pub const fn hpre(&self) -> Hpre

AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.

pub fn set_hpre(&mut self, val: Hpre)

AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.

pub const fn ppre(&self) -> Ppre

APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1.

pub fn set_ppre(&mut self, val: Ppre)

APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1.

pub const fn stopwuck(&self) -> bool

Wake-up from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10).

pub fn set_stopwuck(&mut self, val: bool)

Wake-up from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10).

pub const fn mco2sel(&self) -> Mcosel

Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.

pub fn set_mco2sel(&mut self, val: Mcosel)

Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.

pub const fn mco2pre(&self) -> Mcopre

Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: … Others: reserved It is highly recommended to set this field before the MCO2 output is enabled.

pub fn set_mco2pre(&mut self, val: Mcopre)

Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: … Others: reserved It is highly recommended to set this field before the MCO2 output is enabled.

pub const fn mcosel(&self) -> Mcosel

Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

pub fn set_mcosel(&mut self, val: Mcosel)

Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

pub const fn mcopre(&self) -> Mcopre

Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: … Others: reserved It is highly recommended to set this field before the MCO output is enabled.

pub fn set_mcopre(&mut self, val: Mcopre)

Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: … Others: reserved It is highly recommended to set this field before the MCO output is enabled.