Struct stm32_metapac::syscfg::regs::Cfgr1

#[repr(transparent)]
pub struct Cfgr1(pub u32);

Expand description

SYSCFG configuration register 1

Tuple Fields§

§0: u32

Implementations§

§

impl Cfgr1

pub const fn mem_mode(&self) -> MemMode

Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000

pub fn set_mem_mode(&mut self, val: MemMode)

Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000

pub const fn pa11_rmp(&self) -> bool

PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. 0: No remap (PA11) 1: Remap (PA9)

pub fn set_pa11_rmp(&mut self, val: bool)

PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. 0: No remap (PA11) 1: Remap (PA9)

pub const fn pa12_rmp(&self) -> bool

PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. 0: No remap (PA12) 1: Remap (PA10)

pub fn set_pa12_rmp(&mut self, val: bool)

PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. 0: No remap (PA12) 1: Remap (PA10)

pub const fn ir_pol(&self) -> bool

IR output polarity selection

pub fn set_ir_pol(&mut self, val: bool)

IR output polarity selection

pub const fn ir_mod(&self) -> IrMod

IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:

pub fn set_ir_mod(&mut self, val: IrMod)

IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope:

pub const fn boosten(&self) -> bool

I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high V_DD, setting to 1 for low V_DD (less than 2.4 V).

pub fn set_boosten(&mut self, val: bool)

I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high V_DD, setting to 1 for low V_DD (less than 2.4 V).

pub const fn i2c_pb6_fmp(&self) -> bool

Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub fn set_i2c_pb6_fmp(&mut self, val: bool)

Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub const fn i2c_pb7_fmp(&self) -> bool

Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub fn set_i2c_pb7_fmp(&mut self, val: bool)

Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub const fn i2c_pb8_fmp(&self) -> bool

Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub fn set_i2c_pb8_fmp(&mut self, val: bool)

Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub const fn i2c_pb9_fmp(&self) -> bool

Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub fn set_i2c_pb9_fmp(&mut self, val: bool)

Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I²C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub const fn i2c_pa9_fmp(&self) -> bool

Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I²C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub fn set_i2c_pa9_fmp(&mut self, val: bool)

Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I²C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub const fn i2c_pa10_fmp(&self) -> bool

Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I²C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub fn set_i2c_pa10_fmp(&mut self, val: bool)

Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I²C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I²C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub const fn i2c3_fmp(&self) -> bool

Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I²C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I²C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable

pub fn set_i2c3_fmp(&mut self, val: bool)

Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I²C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I²C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I²C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0: Disable 1: Enable