Struct Ahb1fzr 

#[repr(transparent)]
pub struct Ahb1fzr(pub u32);

DBGMCU AHB1 peripheral freeze register.

Tuple Fields

0: u32

Implementations

impl Ahb1fzr

pub const fn dbg_gpdma0_stop(&self) -> bool

None 0: normal operation. GPDMA channel 0 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 0 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma0_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 0 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 0 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma1_stop(&self) -> bool

None 0: normal operation. GPDMA channel 1 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 1 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma1_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 1 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 1 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma2_stop(&self) -> bool

None 0: normal operation. GPDMA channel 2 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 2 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma2_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 2 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 2 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma3_stop(&self) -> bool

None 0: normal operation. GPDMA channel 3 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 3 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma3_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 3 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 3 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma4_stop(&self) -> bool

None 0: normal operation. GPDMA channel 4 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 4 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma4_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 4 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 4 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma5_stop(&self) -> bool

None 0: normal operation. GPDMA channel 5 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 5 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma5_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 5 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 5 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma6_stop(&self) -> bool

None 0: normal operation. GPDMA channel 6 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 6 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma6_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 6 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 6 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma7_stop(&self) -> bool

None 0: normal operation. GPDMA channel 7 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 7 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma7_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 7 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 7 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma8_stop(&self) -> bool

None 0: normal operation. GPDMA channel 8 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 8 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma8_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 8 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 8 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma9_stop(&self) -> bool

None 0: normal operation. GPDMA channel 9 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 9 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma9_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 9 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 9 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma10_stop(&self) -> bool

None 0: normal operation. GPDMA channel 10 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 10 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma10_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 10 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 10 is frozen while CPU is in debug mode.

pub const fn dbg_gpdma11_stop(&self) -> bool

None 0: normal operation. GPDMA channel 11 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 11 is frozen while CPU is in debug mode.

pub fn set_dbg_gpdma11_stop(&mut self, val: bool)

None 0: normal operation. GPDMA channel 11 continues to operate while CPU is in debug mode. 1: stop in debug. GPDMA channel 11 is frozen while CPU is in debug mode.

Trait Implementations

impl Clone for Ahb1fzr

fn clone(&self) -> Ahb1fzr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Ahb1fzr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Ahb1fzr

fn default() -> Ahb1fzr

Returns the “default value” for a type.

impl PartialEq for Ahb1fzr

fn eq(&self, other: &Ahb1fzr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ahb1fzr

impl Eq for Ahb1fzr

impl StructuralPartialEq for Ahb1fzr